jnk0le / xteic Goto Github PK

instead of lazy stacking for higher efficiency.

executed after stacking of integer registers amortized irq entry overhead

reorder bits or #2

psABI makes it a mirror of integer, reshuffle for more efficient #10/IPRA

reduce bits for addressing, reduce contention with other custom extensions

move a6,a7 to x20,x21 and add x22,x23 as temporaries

no longer aligns with standard zcmp[e] reglist.
extra temporaries shouldn't have negative impact wrt IPRA

loses straightoforward "increase level only by csrsi/csrci" feature.

total 5, priority + nesting priority bits possible by csrwi

unlike other gpr registers, sp can be operated by cm.push/cm.pop/c.*sp instructions

cannot swap sp with teic_swpspm due to nesting

less eficient code, probably nicer to setup thread stack (and u mode) #5

ARM synchronizes only cpsid i.
According to freeRTOS writes to basepri are also not synchronized

what should be a naming for privileged/volume II replacement

push/pop of remaining integer and fp registers through a0/a1 as base

#26 no more necessary
Requires additional csrrw (atomic swap for precomputed next TCB, 2 for typical way), no overhead (or -1 for atomic swap) when no shadow regs are present

some signals forwarded to "external" irq controller #20, #13

rv32e has a large gap here

?

in software

unrecoverable, exceptions, other returnable + reserved for startup

as optional ext

24 vs 32 bit counter

needs to be an NMI
in thread state only

use integrity/illegal instr ones

frees 1 NMI vector entry

more consistent with current definitions used all over the standard extensions

ensure there is no race cond

hidden state to track if only n4 occured?

?

• certain ranges only
• certain nesting levels only
• whole regfile
• etc

requires extra mechanism to access shadowed registers

register content upon irq entry implementation specified