Extended configurability about vhdl-style-guide HOT 16 OPEN

Afternoon @LarsAsplund

I am currently away from a computer for the next three weeks, but I can answer some of these questions.

1. It appears there is no rule to force spacing before the assignment operator in port and generic maps. This is a little puzzling to me as I would expect one to exist. I will work on adding a rule when I return sometime after June 2nd.

2. Have you checked the configuration of rule signal_006? There is an option to set the spacing to 1. The default is at least one space to allow for alignment.

3. Have you checked the configuration of rule if_009? It handles alignment of multiline conditions in if expressions. If you disabled all the alignment rules using via a group, You can enable that rule invidually.

Regards,

--Jeremy

from vhdl-style-guide.

I'll respond here since I am the "active" user of this here at the moment.

1. It appears there is no rule to force spacing before the assignment operator in port and generic maps. This is a little puzzling to me as I would expect one to exist. I will work on adding a rule when I return sometime after June 2nd.

Appreciate it! :)

2. Have you checked the configuration of rule signal_006? There is an option to set the spacing to 1. The default is at least one space to allow for alignment.

We have that one enabled, it doesn't seem to fix the colon around the signal keyword when used in hierarchical references.

3. Have you checked the configuration of rule if_009? It handles alignment of multiline conditions in if expressions. If you disabled all the alignment rules using via a group, You can enable that rule invidually.

We have that rule enabled, with align_left: yes and align_paren: no, it still seems to put the next row of statements on the same level.

from vhdl-style-guide.

Morning @ru551n ,

We have that one enabled, it doesn't seem to fix the colon around the signal keyword when used in hierarchical references

I reviewed the rule and it should work with hierarchical references. Could you post the output of the following command:

vsg -rc signal_006

We have that rule enabled, with align_left: yes and align_paren: no, it still seems to put the next row of statements on the same level

Maybe I misunderstood the original question. Is the issue the indenting is not working or the structure of the expression (adding or removing carriage returns) the issue?

--Jeremy

from vhdl-style-guide.

I reviewed the rule and it should work with hierarchical references. Could you post the output of the following command:

λ vsg -rc signal_006 -c .vsg.yaml
{                                
  "rule": {                      
    "signal_006": {              
      "indent_style": "spaces",  
      "indent_size": 2,          
      "phase": 2,                
      "disable": false,          
      "fixable": true,           
      "severity": "Error",       
      "number_of_spaces": 1      
    }                            
  }                              
}                                

from vhdl-style-guide.

Afternoon @ru551n ,

It appears the rule is configured correctly for a single space. I will need to get to a computer before I can debug any further. I will be back from vacation on June 2nd and will take a look at these issues shortly after.

Regards

--Jeremy

from vhdl-style-guide.

Morning @ru551n ,

I have added two new rules to enforce whitespace before port map and generic map assigment operators to branch issue-1170. This should address the first issue. When you get a chance could you check it out on your end and see if it is working for you.

For the second issue, I have the following code snippet:

  1 architecture rtl of fifo is
  2
  3   signal dut.foo      : std_logic;
  4
  5 begin
  6
  7 end architecture rtl;

I used the following configuration file:

  1 "rule": {
  2   "global": {
  3      "disable" : true
  4   },
  5   "signal_006": {
  6      "disable" : false,
  7      "number_of_spaces" : 1
  8   }
  9 }

when I run vsg against the file using the configuration I get the following code:

  1 architecture rtl of fifo is
  2
  3   signal dut.foo : std_logic;
  4
  5 begin
  6
  7 end architecture rtl;

I must be missing something as rule signal_006 seems to be enforcing a single space before the colon. Could you post a snippet that shows the issue you are seeing?

Regards,

--Jeremy

from vhdl-style-guide.

Afternoon @ru551n ,

Is there a chance you could post a snippet of the third issue? I have my test example and it seems to be working as expected:

  1 architecture rtl of fifo is
  2
  3   signal dut.foo      : std_logic;
  4
  5 begin
  6
  7   PROC_1:process
  8
  9   begin
 10
 11     if condition_a and condition_b then
 12     elsif condition_a and
 13                         condition_b then
 14     end if;
 15
 16   end process PROC_1;
 17
 18 end architecture rtl;

with this configuration:

  1 "rule": {
  2   "signal_006": {
  3      "disable" : false,
  4      "number_of_spaces" : 1
  5   },
  6   "if_002": {
  7     "parenthesis": "remove"
  8   },
  9   "if_009": {
 10     "align_left": true,
 11     "align_paren": false
 12   }
 13 }

yields:

  1 architecture rtl of fifo is
  2
  3   signal dut.foo : std_logic;
  4
  5 begin
  6
  7   proc_1 : process is
  8   begin
  9
 10     if condition_a and condition_b then
 11     elsif condition_a and
 12       condition_b then
 13     end if;
 14
 15   end process proc_1;
 16
 17 end architecture rtl;

I feel I am missing something on the last issue.

--Jeremy

from vhdl-style-guide.

Morning @ru551n and @LarsAsplund ,

Just wanted to ping you on this issue to see if we can move this forward.

Thanks,

--Jeremy

from vhdl-style-guide.