iobundle / iob-lib Goto Github PK

HWDEFINES+=A=1

yields

`define PREFIX_A 1

does it work ?

If I changed a file in the core or lib repos will only these files be copied to build lib a not trigger unnecessary compilations?

iob, axi(lite, stream), ahb, apb, etc

LIB seems to include iob_clkrst_port.vh and iob_clkrst_portmap.vh even though it is not used.

mkregs.py is unnecessarily complicated by having a wdata signal for each input register.

For example, IOB_I2S_TDM_TXBCLK_POLARITY_wdata isn't needed, one can use wdata simply. A different name for the same wire is being created for each write register for no reason.

Now, IOB_I2S_TDM_TXBCLK_POLARITY_en is important because it selects the register to write. Hence the instance after the correction should be:

`IOB_WIRE(IOB_I2S_TDM_TXBCLK_POLARITY, 1)
iob_reg #(.DATA_W(1), .RST_VAL(0))
iob_i2s_tdm_txbclk_polarity (
.clk (clk),
.arst (rst),
.rst (rst), //SERIOUS MISTAKE !!!

//this is unrelated to this issue but DO NOT connect the async reset signal to anything other than flip-flop async reset inputs!! If the sync reset is not being used, simply tie it to 0:
.rst (1'b0)

   .en         (IOB_I2S_TDM_TXBCLK_POLARITY_en),
   .data_in    (wdata[1-1:0]),
   .data_out   (IOB_I2S_TDM_TXBCLK_POLARITY)

);

Simplify mkregs.py and save future maintenance.

when using iob_fifo_async module, for (R_DATA_W > W_DATA_W) and (W_DATA_W == R_DATA_W) cases, we get the following warnings:

../src/iob_fifo_async.v:224: warning: implicit definition of wire 'clk_i'.
../src/iob_fifo_async.v:225: warning: implicit definition of wire 'cke_i'.
../src/iob_fifo_async.v:226: warning: implicit definition of wire 'arst_i'.

• the clk_i, cke_i and arst_i wires are defined in a generate case scope that is not available for iob_asym_converter.vs scope

These warning should be fixed when we perform verilog generates in python

A failed attempt to enable the incremental setup.

To make this possible, generation scripts should specify the destination directory.
Another improvement is to infer what to generate from the output file name since the name of what to generate is part of the output file name anyway.

the _swreg_gen instance portmap should use

.iob_avalid_i(iob_avalid_i), etc

Not

.iob_avalid_i(iob_avalid), etc

Rationale: the conversion to a standard interface (eg, AXI LITE) should always be done in an external wrapper

Affected modules:
asym_converter
fifo_sync
fifo_async

These tests have been removed by the Makefile revamp on June/8/2023

and let it respond to requests only

`include header statements should be replaced by the contents of the header itself during setup.

Motivation (Problem)

-- every time I need to add or modify a register, I forget the meaning of the fields

Side Benefit

--without parse, the code will be much simpler

Objective

change

IOB_SWREG_W(TXSOFT_RST, 1, 0, -1, 0, 1) //Soft reset.

to

{'Name': 'TXSOFT_RST', 'Type': 'W', 'Width': 1, 'ResetValue', Address: -1, 'AdressWidth': 0, 'AutoLogic': 1}

So, I know the fields I am writing all the time, even if I have to copy one of the existent

Use a .json file

Place an example mkregs.json in iob-lib's root

Priority: HIGH

causes vcd file transfer to recommence

Probably related to the removal of the header parse by the assignee and put back by the issue author.

Note that header_parse was moved from mkregs.py to verilo2tex since it is only used in the latter.

However, either the headers passed are wrong, or another problem.

Expressions should be evaluated when they do not contain variables

This is caused by

ifndef VH_IOB_I2S_TDM_CONF_VH define VH_IOB_I2S_TDM_CONF_VH

...

`endif // VH_IOB_I2S_TDM_CONF_VH

Fix suggestions

1. are the above necessary in Verilog? I have never noticed that it is, but I may be wrong

2. improve hw_defines to deal with it.

Maybe

`define VH_IOB_I2S_TDM_CONF_VH 1

solves the problem

This script is wrongly named and should be converted to a python script (because python3 is called in most lines ) and moved into software/python temporarily

Correct name: genus2tex.py (it only supports this tool and not asics in general)

Later, when there is a proper asic flow it should be moved to the build directory

calling the constructor should be enough for trigger setup

this issue has high priority as it is very confusing having to do both

the instance should connect to top-level ios, not internal wires

.iob_avalid_i(iob_avalid_i)

not

.iob_avalid_i(iob_avalid)

This is because conversion to the interface types should only occur in the wrappers

Issue:
Each interface defined in the .py file requires a new set of parameters. Currently, those parameters have to be defined by hand. It would be nice to be able to define the parameters in the python setup. If not defined, the wires would be generated with parameters like they are now.
Example:

  {"interface": "peripheral_axi_wire", "AXI_ID_W": "1"},

it would be best to have a single .tcl file that compiles the design instead of a sequence of steps in the makefile
(for Vivado this seems to be the case)

how can we distinguish between netlist (qxp) compilation and system compilation to run the design on an FPGA device?

for example

wire [BE_ADDR_W-1:0] be_iob_addr.

create this concept and replace

//PHEADERS -> IOB_PRAGMA_PHEADERS
//PWIRES -> IOB_PRAGMA_PWIRES
//PORTS -> IOB_PRAGMA_PPROTMAPS

a new one
IOB_PRAGMA_PERIPHS
to insert peripheral instances instead of doing it before end module

add to if_gen.py

should output to .vs

Currently, in IOb-SoC-opencryptolinux in the Setup phase the software of the iob-uart is copied. The iob-uart is only used in simulation, therefor the software is not required. It causes conflicts with the iob-uart16550 software. Even after renaming all the iob-uart16550 functions so that these have a different name from the iob-uart functions.

TXFIFO_LEVEL = {rw_type="R", nbits=1+param['TXFIFO_ADDR_W'], rst_val=0, addr=-1, addr_w=1, autologic=true, description="Number of filled positions in the FIFO."}

Mkres.py generates hard code and comprises instance pre-silicon confugurability!

@classmethod
def _setup_block_groups(cls):

if the iob-soc groups not preset it gives an error

when the tester runs iob_soc.py, it thinks the iob_groups are for the tester and complains about not having such groups

self explanatory

because of _i and _o

setup now runs from the core directory and not from the lib directory

Hence, for all hardware.mk files, the above prefix must be added to all lib files to be copied to the core build directory. This has already been done for the hardware.mk lib files used by iob-cache

See hardware/ram/iob_ram_sp/hardware.mk for instance. Test and update iob-uart after this is done.

otherwise, IOs in internal modules will inadvertently appear in the doc

another advantage of having this new pragma is that verilog2tex will work regardless if the user chooses to use the lib IO macros or not

if you decide to implement test in i2s please

--no-overlap

Add driver documentation support using Doxygen.
See UART proof of concept for a working example.
Related issues: IObundle/iob-uart#48, IObundle/iob-cache#214

_setup_regs means the module wants registers

so the necessary sources should be copied

no need to include them in the module

same as #493 but for python

currently only hw_modules possible but some modules are only to be used for fpga or simulation

same as #493 for C

refer to PR

should be created automatically from meta parameter

for example, in i2s if I just leave the top level .v file and the conf.vh file it does not work. Why?

cache needs two additional files containing //BLOCK pragmas

for example in the uart

def _run_setup(cls):
# Hardware headers & modules
iob_module.generate("iob_s_port")
iob_module.generate("iob_s_portmap")
iob_lib.setup()
iob_utils.setup()
iob_clkenrst_portmap.setup()
iob_clkenrst_port.setup()
iob_reg.setup()
iob_reg_e.setup()

Submodule functions x.setup() are non-sensical as one just wants the sources and not set them for simulation or fpga

It should be
iob_lib.cpy_src()
not
iob_lib.setup()

In _swreg_gen #(

it is
...
wire [16-1:0] VERSION;
...
.VERSION_i (VERSION),
...

but it should be
.VERSION_i (16'd`IOB_NAME_VERSION),

create a new type for if_gen

this will help working with external memories

iob_clkenrst_port and iob_clkenrst_portmap should be included in all cores and used in the documents generation instead of io field in _setup.py

Upon Setup, run Veritable to check the Verilog code inside the current repo and produce an error if not conformant.

The user should use this error to fix the Verilog files in the repo until Setup is not giving this error anymore.