Is your feature request related to a problem? Please describe.
Similar to the ability to treat structs as signals in SystemVerilog.

Describe the solution you'd like
The LogicStructure object would extend Logic and could take a list of Logic in its constructor. These LogicStructures could then be used just like a Logic for assignments, conditional assignments, elements of interfaces, inputs/outputs of modules, etc.

The implementation of overridden Logic methods would simply loop through the collection of Logics.

Down the road, this could potentially map to a generated SystemVerilog struct or be used to implement arrays convertible to SystemVerilog.

Describe alternatives you've considered
An alternative is to just let each user individually determine a convenient way to group signals. Probably many users would implement it similarly and have a same set of base requirements.

It would be nice to have a mixin that lets ROHD know it will fail to synthesize a Module. That way if an architectural model or BFM has a Module used in a design, any generation of output can be flagged.

The default implementation for If, Iff, etc. take lists of Conditionals as inputs, which can be excessively verbose in cases where there is only one Conditional. Adding a special constructor (e.g. something like Iff.s) which takes a single Conditional could make simple code look cleaner.

Describe the bug
Default behavior for Interface.connectIO passes inputTags and outputTags as optionally null directly to getPorts , which then returns all ports.

To Reproduce
Call connectIO with no inputTags nor outputTags on an Interface which has at least one port.

Expected behavior
If no tags are provided, it should not connect anything. Maybe should throw an exception if neither is provided?

Actual behavior
Exception "Already defined a port with name..."

Describe the bug
Testbench code (e.g. BFMs) are likely to do things like trigger a put or inject on the next clock edge. The current behavior of an inject at the end in outOfTick phase will keep the pending injected action sitting there until the Simulator starts the next tick. This is not really intuitive and should be changed.

Expected behavior
inject should actually happen as soon as possible, as documentation indicates

Actual behavior
injected actions sit there waiting for a while

Describe the bug

Generated SystemVerilog from ROHD will be unsized like 0 or 15 instead of with an explicit size like 2'b0 and 16'd15. This can cause anything from a lint failure to a swizzling width mismatch/misalignment.

To Reproduce

Generate SystemVerilog with constant value assignments using Const.

Expected behavior

All constants are sized.

Actual behavior

No constants are sized.

Motivation

See discussion on this pull request:
#71 (comment)
Which mentions this StackOverflow answer:
https://stackoverflow.com/questions/50320220/in-dart-whats-the-difference-between-list-from-and-of-and-between-map-from-a

Desired solution

Rename the from... methods in LogicValue and LogicValues to of...

Alternatives considered

Existing from doesn't affect functionality, but is inconsistent with the rest of Dart conventions

Is your feature request related to a problem? Please describe.
To build a LogicValues using existing constructors from a bool can be a bit verbose:

LogicValues.from([myBool ? LogicValue.one : LogicValue.zero]);

Describe the solution you'd like
It would be nice to do something like:

LogicValues.fromBool(myBool);

Something similar in LogicValue would be nice too.

Describe the bug

Zero width signals get created as 1 bit signals in generated SystemVerilog

To Reproduce

Make a zero-bit port for a module and generate the SystemVerilog

Expected behavior

No signal added

Actual behavior

1 bit signal added

Useful for assembly of components, analog/MSV, etc.

Motivation

pub.dev gives extra pub points for following package recommendations for examples. This also makes the example show up in the pub.dev site.
https://pub.dev/packages/rohd/score

Desired solution

https://dart.dev/tools/pub/package-layout#examples

Alternatives considered

Examples are currently organized by name, but not following conventions.

Additional details

Probably the "counter" example should be the main one.

Motivation

It's confusing that there's slice for Logic and getRange for LogicValues. Also, that Logic has width and LogicValues has length. These, and maybe some other areas, should be made more consistent to reduce confusion. In some cases, maybe both should have both options (e.g. slice and getRange might be more useful in different scenarios but to both), and in other cases one should probably be deprecated and eventually removed.

Desired solution

Consistency between LogicValues and Logic where possible.

Alternatives considered

Leave things inconsistent. Original motivation was that LogicValues acts like a List and Logic acts more like SystemVerilog, but that might not be the right approach.

Additional details

Open to other suggestions!

Describe the bug
When any bit is 1, unary OR should return 1. When any bit is 0, unary AND should return 0. Invalid bits violate these rules.

To Reproduce

        expect( // and - invalid
          LogicValues.fromString('010x').and(),
          equals(LogicValue.zero)
        );
        expect( // or - invalid
          LogicValues.fromString('010x').or(),
          equals(LogicValue.one)
        );

Expected behavior
Tests should pass

Actual behavior
Tests fail since one bit is invalid.

Additional context
Found by @kimmeljo in #21

Describe the bug

If a signal that directly or indirectly triggers flop sampling is consumed within the procedural list of Conditionals, then the signal used for computation is the signal from before the edge. This causes improper behavior for situations like a flop with asynchronous reset.

To Reproduce

For example:

FF( (clk | reset), [
      If(reset, then:[

Expected behavior
Behavior should match SystemVerilog, reset should be the value that triggered the sampling.

Actual behavior
Reset is the value immediately before the trigger.

Motivation

It would be nice to use FlipFlop with a reset signal (optionally synchronous or asynchronous)

Desired solution

Add optional named parameter(s) to FlipFlop that, when specified, add reset behavior.

Alternatives considered

People can already achieve this using the Sequential block, but FlipFlop is convenient.

Describe the bug

If port names are uniquified, then the getPorts function for specific tags fails to find the associated ports because it searches based on port.name instead of the interface's port name.

To Reproduce

Uniquify port names and then try to list them with getPorts()

Expected behavior

Uniquified ports are still discoverable.

Actual behavior

No ports are returned

Is your feature request related to a problem? Please describe.
ROHD interfaces already support hierarchical interfaces, but there is no documentation or examples covering how to do it.

Describe the solution you'd like
Add a section in the README that discusses hierarchical interfaces. Perhaps some examples and unit tests are valuable as well.

Describe the bug

The algorithm that determines which Modules are within which other Modules via input and output tracing has a bug which reveals itself in certain situations when outputs depend on other outputs of the same Module.

To Reproduce

class TopModule extends Module {
  TopModule(Logic a) {
    a = addInput('a_top', a);
    SubModule(a);
  }
}

class SubModule extends Module {
  SubModule(Logic a) {
    a = addInput('a', a);
    var b = addOutput('b');
    var c = addOutput('c');
    b <= a;
    c <= b;
  }
}

void main() {
  test('out depends on out', () async {
    var mod = TopModule(Logic());
    await mod.build();
  });
}

Expected behavior

Builds properly

Actual behavior

Exception due to "Violation of input/output rules". Fortunately ROHD identified something was wrong rather than generate something invalid.

Additional details

Please paste the output of dart --version

$ dart --version
Dart SDK version: 2.16.1 (stable) (Unknown timestamp) on "linux_x64"

Please paste the contents of your pubspec.yaml file and identify the version of ROHD you're using
Unchanged for ROHD

Similar to SystemVerilog: http://www.verilogpro.com/systemverilog-unique-priority/

Motivation

With the current implementation, if a signal is being listened to for changed, then it triggers an action on every preTick and postTick of the simulator. This is probably less efficient than it could be for simulator performance.

Desired solution

It could be more efficient if listening to preTick was eliminated and postTick was only listened to after a glitch which caused a change.

Alternatives considered

Leave it as-is.

Motivation

pub.dev gives extra pub points if the code is formatted using dart format
https://pub.dev/packages/rohd/score

Desired solution

https://dart.dev/guides/language/formatting

Alternatives considered

Just manually formatting everything

Additional details

After running the format tool, it's worth reviewing the changes it did. If we want to keep the format nice permanently, we can add it as a CI check in GitHub Actions. Also worth recommending in IDE to enable format on save.

File operations might be a significant source of slowdown when running a simulation.

Something similar to TL-Verilog: https://www.redwoodeda.com/tl-verilog

Describe the bug

The waveform generated by the ROHD simulator doesn't have same behavior like other simulators such as modelsim.
I need some helps to clarify this bug.

To Reproduce

Full dart code file
delay_signal.txt
Please change the file extension to dart.
Core part:

    List<Logic> _z = List<Logic>.generate(depth, (index) => Logic(width: bitWidth));

    var out = addOutput('out', width: bitWidth);

    List<ConditionalAssign> _zList = [_z[0] < inputVal];
    for(int i = 0; i<_z.length;i++){
    // for(int i = _z.length-1; i>=0;i--){
      if(i == _z.length-1){
        _zList.add(out < _z[i]);
      }else{
        _zList.add(_z[i+1] < _z[i]);
      }
    }

    Sequential(clk, [
      IfBlock([
        Iff(en, _zList
        ),
        Else([
          out < 0,
        ])
      ])
    ]);
  }

Steps to reproduce the behavior:

1. Run a simulation with ROHD
2. See the waveform from gtkwave

Expected behavior

The input value should be appeared in the out value after few clock cycles.

Generated systemverilog:

//  sequential
always_ff @(posedge clk) begin
  if(en) begin
      s0 <= inputVal;
      s1 <= s0;
      s2 <= s1;
      s3 <= s2;
      s4 <= s3;
      out <= s4;
  end   else begin
      out <= 0;
  end 
end

modelsim/others result: <- Correct result

ROHD result:

Actual behavior

The out value directly equal to the input val at the first positive edge.

Additional details

Please paste the output of dart --version

> dart --version
Dart SDK version: 2.15.1 (stable) (Unknown timestamp) on "linux_x64"

Please paste the contents of your pubspec.yaml file and identify the version of ROHD you're using

name: delay_signal
description: A simple command-line application.
version: 1.0.0

environment:
  sdk: '>=2.14.3 <3.0.0'


# dependencies:
#   path: ^1.8.0
dependencies:
  rohd:
    git:
      url: https://github.com/intel/rohd.git
      ref: main


dev_dependencies:
  lints: ^1.0.0

Motivation

Right now most operations in ROHD are unsigned. Less than, greater than, etc. would be a lot more convenient with some built in signed support.

Desired solution

Allow operations to be performed using signed or unsigned math optionally.

Alternatives considered

Letting users do their own signed math is unnecessary overhead.

Describe the bug
Multiple ticks can execute simultaneously, which can cause multiple event triggers since it violates the rules of Simulator phase ordering. For example, multiple Logic.changed events can occur in the same tick for a single transition.

To Reproduce
This test reproduces:

  test('clk edge counter', () async {
    var clk = SimpleClockGenerator(10).clk;
    var b = Logic();
    
    bool val = false;
    clk.negedge.listen((event) async {
      b.inject(val);
      val = !val;
    });

    var uniquePosedgeTimestamps = <int>{};
    var count = 0;
    clk.posedge.listen((event) {
      uniquePosedgeTimestamps.add(Simulator.time);
      count++;
    });

    Simulator.setMaxSimTime(100);
    await Simulator.run();

    expect(count, equals(uniquePosedgeTimestamps.length));
  });

Expected behavior
Single event trigger per event.

Actual behavior
Multiple event triggers per event in some situations.

Motivation

Currently, you can only connect each Logic to one source ever, and then it cannot be reassigned to connect to something else. There are cases where it might be nice to reassign connectivity.

Desired solution

In Logic._assertConnectable, there's a check that _srcConnection is null. We can remove this check, but it requires some additional safety around that change for the rest of the assumptions of ROHD to be accurage.

Alternatives considered

Consider keeping it as strictly one-time-connectivity, maybe it encourages cleaner designs?

Additional details

Since hierarchy is based on signal connectivity, changing the connectivity could potentially require a rebuild (also currently disallowed). This might be a substantial change.

Describe the bug
For _SmallLogicValues and _BigLogicValues, when doing an operation with overflow (e.g. +) the _value and _invalid could overflow and are not properly masked.

To Reproduce

      expect( // + overflow
        LogicValues.fromString('1111') + LogicValues.fromString('0001'),
        equals(LogicValues.fromString('0000'))
      );

Expected behavior
Test passes equality check

Actual behavior
Failure, internal representation is 10000

Additional context
Found by @kimmeljo in his unit test in #21

If you do a put on a signal right after attaching a Dumper, it will not update the initial values that get logged into the VCD, so the waveform looks like z even if the functional simulation has a different value there.

An easy way to fix is probably to write initial values only after the first tick occurs.

Motivation

The current toString for Logic just gives the type, name, and width. It could be more insightful than that.

Desired solution

It could show more information including the current value of the signal, the hierarchy where it is located (if available), and maybe some additional stuff.

Alternatives considered

Maybe it's nicer short and simple?

Motivation

SystemVerilog assertions are valuable for design and verification. It would be nice to have assertions in ROHD that give similar functionality, but that are also "synthesizable" to behavioral SystemVerilog so that simulations of generated code can also benefit from the assertions.

Desired solution

An Assertion type that acts like an assert or Exception in Dart, but is also synthesizable to the generated output representation.

Alternatives considered

Existing assertions and exceptions in Dart are already nice, but not synthesizable to the generated representation.

Motivation

There are cases where you want to compare two LogicValues values for some bits, but not all bits. It would be nice to support an equality check that enables a comparison of two LogicValues where any x is treated as a "don't care if this bit is equal". Some thought would need to be put into whether only one side of the comparison should consider x as don't care or both sides, or maybe that should be configurable. This feature is similar to a casez but for values instead of hardware.

Desired solution

Add a function for comparison with don't care to LogicValues.

Alternatives considered

Let users implement this functionality themselves as needed.

The implementation for Mux maps to a SystemVerilog ternary operator (? :). Chaining together a bunch of ternary operators in SystemVerilog is a common pattern, but requires nested Muxs and lots of parentheses in ROHD. A module that supports chained mux behavior would be nice.

Motivation

It's annoying to convert a LogicValue to LogicValues in cases like swizzling together the two types.

Desired solution

It could be as simple as adding a toLogicValues() function to LogicValue. Or perhaps a named constructor for LogicValues called ofLogicValue.

Alternatives considered

Current solution requires LogicValues.of([myLogicValue]), which is a little verbose and annoying to create a list.

Motivation

The swizzle and rswizzle operations on Logic are useful, but there's no equivalent for LogicValues. It would be nice to have similar functionality available for LogicValues.

Desired solution

Perhaps some sort of Swizzleable type or something so that swizzle and rswizzle can directly be reused as parameterized functions instead of reimplementing again? For example:

SwizzleableType swizzle<SwizzleableType extends Swizzleable>(List<SwizzleableType> components) => ...

Alternatives considered

Available current solution is just doing things like a bitwise OR, but that's less convenient. A specific function or constructor for LogicValues could work too.

Just like what's in Logic, put that in LogicValues

Motivation

Some exceptions could have improved error messages to help the user identify the issue. For example:
Exception: This signal is already connected.

Desired solution

Error messages should give as much context as possible, for example:
Exception: Signal "x" is already connected to signal "y", so it can't be connected to signal "z".

Is your feature request related to a problem? Please describe.
Support multiple triggers for flops, like in SystemVerilog:

always_ff @(posedge clk or posedge reset)

Describe the solution you'd like
The FF and FlipFlop should have a syntax that accepts a list of signals instead of a single clk signal.

Describe alternatives you've considered
Using something like clk | reset is insufficient because there could be a rising edge of reset during a clock high period.

A convenient operation to check if one Logic is currently equal to any of a list of other Logics, which synthesizes safely to hardware. The operation could be called equalsAnyOf or isIn or something else like that.

Describe the bug
The _driverValueOverrideMap in Conditional uses driver instead of driverInput(driver), causing chained FFs to act like combinational logic instead of flops.

To Reproduce
Chain multiple FF conditional assignments together.

Expected behavior
Match SystemVerilog behavior

Actual behavior
Combinational delay instead of flops

Across applicable areas (gates, Logic, LogicValues, etc.)

The current parameter append in Interface.connectIO adds a String to the end of a port name to help uniquify it. It would be better and more generic to take in a String Function(String original) as a parameter to connectIO.

Describe the bug

Swizzling an empty list causes an "invalid radix-2 number" type of exception to get thrown since down the line there is a blank string passed to int.parse.

To Reproduce

<LogicValues>[].swizzle()

Expected behavior

An empty list should return a zero-width value.

Actual behavior

An exception related to the underlying implementation of swizzle is thrown, confusing users.

Right now, Module has a method generateSynth which uses a SynthBuilder and SystemVerilogSynthesizer to generate SystemVerilog file contents. It would be better if Synthesizer had a function that consumes Modules directly and returns/generates the file contents. A new Synthesizer should not require a new method in Module.

Motivation

Padding width of signals (either signed or unsigned) is a bit too verbose. It would be nice to be able to extend/pad Logic and LogicValues.

Desired solution

Operation on Logic and LogicValues that return zero extended and sign extended versions with larger width.

Alternatives considered

Existing solution requires using something like swizzle.

Motivation

Build-time uses signal connectivity to derive hierarchy, so new connections after build could cause strange mismatches between generated code and simulation behavior. Similarly, if signals are connected after the simulation has started, the behavior of the hardware could change. It's probably best to add some checks to prevent this type of things from happening.

Desired solution

Prevent signal connectivity from changing after build and simulation has begun.

Alternatives considered

Leave it as-is, with users responsible for any weird decisions they make.

Lots of "boring" signals like Consts, unnamed signals, simple gates, InlineVerilogs, etc. get dumped by the Dumper. This slows down the simulations and doesn't add much value.

Motivation

In SystemVerilog, you can make a binary number like 6'b11_00_11 to separate portions of the binary. It would be nice to do that with ROHD.

Desired solution

The bin function automatically removes _ characters from the string before parsing it as binary.

Alternatives considered

Current implementation requires only numbers 0 and 1.

Need special attention around negatives, 64-bit wide, and other corner cases related to the various implementations.

The current implementation of FF._setup() registers to all events from Simulator.preTick and Simulator.clkStable, but this is unnecessarily expensive for simulations where not every FF is toggling every tick.

Could just listen to glitches of inputs to FF, and selectively allow updates to pre-tick values from those glitches based on the simulator phase to avoid the preTick subscription.

The clkStable subscription could be subscribed via first only in cases where it is interesting (a change would occur).