hfyfpga Goto Github PK

clusterv-soc

Quad cluster of RISC-V cores with peripherals and local memory

cmsis_5

CMSIS Version 5 Development Repository

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-test

Unit testing for cocotb

cocotbext-axi

AXI interface modules for Cocotb

cocotbext-eth

Ethernet interface modules for Cocotb

cocotbext-i2c

I2C models for cocotb

cocotbext-pcie

PCI express simulation framework for Cocotb

cocotbext-uart

UART models for cocotb

common_cells

Common SV components

configuration-structure

RISC-V Configuration Structure

constraints

Reusable constraints

core-v-cores

CORE-V Family of RISC-V Cores

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

core_sdram_axi4

SDRAM controller with AXI4 interface

core_usb_cdc

Basic USB-CDC device core (Verilog)

core_usb_fs_phy

USB Full Speed PHY

core_usb_host

Basic USB 1.1 Host Controller for small FPGAs

coremark

CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

cores

Various HDL (Verilog) IP Cores

cores-swerv

SweRV EH1 core

cortex-debug

Visual Studio Code extension for enhancing debug capabilities for Cortex-M Microcontrollers

cortex-m-apps

Create/Collect various applications for ARM Cortex-M devices | 收集各种有意思的ARM Cortex-M例程（如CoreMark、Dhrystone、memtester）

cortex-m-spec

Collection of ARM Cortex-M specification | 收集ARM Cortex-M内核官方手册

cortexm0_soc

Cortex M0 based SoC

cortexm0_soc-1

cortexm0_soc_task

Step by step tutorial for building CortexM0 SoC