fpgasystems / fpga-network-stack Goto Github PK

I just found the dcp file for SmartCamctl. Do you have the source file for it? C file or rtl file are both ok.

Does anyone know how to change the IP address? How to get the TCP port number.

Hi all,

Has anyone tried to build a connection between the board and the Linux kernel TCP stack?

I'm using the board as TCP client, and the Linux as TCP server. I found the Linux is not reacting to the first SYN packet from the board. The board and the server are connected directly with no switch in between.

I suppose I could debug the TCP headers whatnot, but just want to ask whether anyone has the same experience. Thanks.

Here is the SYN packet from tcpdump. The board is 192.168.1.8. The server is 192.168.1.71.

11:37:33.578934 IP (tos 0x0, ttl 64, id 0, offset 0, flags [none], proto TCP (6), length 48)
    192.168.1.8.32768 > 192.168.1.71.60000: Flags [S], cksum 0x32ff (correct), seq 1445134768, win 65535, options [mss 4096,wscale 2,eol], length 0
        0x0000:  0b0a 0908 0706 0605 0403 0201 0800 4500  ..............E.
        0x0010:  0030 0000 0000 4006 f728 c0a8 0108 c0a8  .0....@..(......
        0x0020:  0147 8000 ea60 5623 01b0 0000 0000 7002  .G...`V#......p.
        0x0030:  ffff 32ff 0000 0204 1000 0303 0200       ..2...........

Could you share me the dcps which can be opened by vivado2019.1 ?

I have 10G/25G Ethernet Subsytem 3.1 which is integrated with bit older version of toe. I would like to know if this MAC IP would work with this toe/earlier version of toe on Alveo u280.

thanks and regards,
Ishtiyaque
[email protected]

If possible, how about trying to upgrade the project to support 100G Ethernet MAC?
I can ask my friend to make two PCB with XCZU19EG (built-in 100G Ethernet MAC hard IP). and let's make it fun.
[email protected]
:- )

Hello, I want to try out this project for my research project.

I want to run some TCP/IP stack benchmark on my vcu118 board, but it seems like there are multiple repos that contain TCP/IP stacks in https://github.com/fpgasystems/(Coyote, Vitis_with_100Gbps_TCP-IP, this repo, and etc), and I am quite confused which one is usable and which one is not.

Can you recommend the right repository to start with, if I want to run perf_tcp or repoduce numbers from Vitis_100Gbps_TCP_benchmark?

How to use RoCEv2?
Could you please give an example?
Thank you.

Toe's tests(toe_tb) and implementations are mismatched and do not seem to be implemented completely, especially in the case of mode1 and mode 2.
When testing the RX side, the test in the testVector folder, part of the checksum is incorrect.
In addition, the test case of the TX side and the test case of the mode2 are not given. Can you upload this part of the use case?
The test data and golden used for Toe_script_probably_obsolete.py are also not been uploaded.
Can you provide these test cases ?
Thank you.

Hi,

I adapted your code to run on the KC705 at 10Gbps.
I tested ping, echo server, PC to FPGA custom data transfer and it work fine so far.

I have however an issue when the FPGA send the data to the PC.

I wrote a server (FPGA) that wait for a connection from a PC application and then send test data . (thing iperf3 with option -R i.e. server send) . I make sure I use the txMeta interface to reserve space before seeding a packet, but otherwise I send as fast as I can.

This work for a couple packet then the FPGA stall and stop to send packet and on wireshark I can see a lot on TCP WINDOWS UPDATE and it seen the PC cannot keep with the FPGA.

On chipscope, I stall on the SEND_PACKET state and more specifically on a txData.write() blocking statement.

My question is the stack support changing windows size ?

Hi @dsidler ,

I'm using the rocev2 IP and I'd like to test its bandwidth or latency. However, I don't see how to access the QP states so as to determine when RDMA requests are finished.

Is it possible to access those QP states from outside the rocev2 IP?
How did you determine when RDMA requests are finushed when you did the benchmarks in the StRoM paper?

Best,
Terry

Line 372: " bool stream_empty[1]; " in the function insertChecksum should be " bool stream_empty[2];"

Hi,
The scripts folder have been deleted and the starting guide suggests to run the make_tcp_ip script. But this file does not exists anymore since the June commit. I would like to create the VC709 project for example and there is some problems in those scripts due to the change in the repository and scripts name.

Is it possible to up to date the starting guide plz ?

Hi David,

How is out of order segments processed in current version toe? It seems like the out of order segments are just dropped. Could you help to confirm it?

Thanks.

Zhe

I would like to know if this design can be targeted on Alveo u50 xilinx_u50_gen3x16_xdma_5_202210_1 platform?

Hi,

I would like to use the TCP/IP stack for VCU1525 and need an example design for a test. However, the top-level module (tcp_ip_top) has not been updated with the implementation of the network stack module.

Is it possible to have an updated and simple example design with basic applications like an echo server?

Best

Not sure if some directories or files are updated to different versions causing this error.
But we found in the *project.tcl , it sets the src_dir to "rtl", but there is no "rtl", only "hdl" is available.
After fix the src_dir and some minor error (like no NUM_TCP_CHANNELS defined in network_stack.v)
we started to do synthesis, but if failed with errors like below, we checked the network_stack.v and found the
tcp_ip_top.v instantiates a "network_stack" with different in/out ports.

[Synth 8-2916] unconnected interface port 's_axil' ["/mnt/projects/fpga-network-stack-master/hdl/ultraplus/vcu118/tcp_ip_top.v":369]
[Synth 8-6156] failed synthesizing module 'network_stack' ["/mnt/projects/fpga-network-stack-master/hdl/common/network_stack.sv":36]

Trying to build from source
Ubuntu 22.04
Vivado 2022.2

Steps to reproduce

1. mkdir build && cd build
2. cmake .. -DFNS_PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 -DFNS_DATA_WIDTH=64 -DFNS_ROCE_STACK_MAX_QPS=500
3. make ip

Getting error:

ERROR: [HLS 207-3776] use of undeclared identifier 'FNS_ROCE_STACK_MAX_QPS' (/home/test/source/learn/xilinx/tcp-ip/fpga-network-stack/hls/ethernet_frame_padding/../fns_config.hpp:5:26)
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 1.73 seconds. CPU system time: 0.16 seconds. Elapsed time: 0.95 seconds; current allocated memory: 0.000 MB.
 
    while executing
"source /home/test/source/learn/xilinx/tcp-ip/fpga-network-stack/build/hls/ethernet_frame_padding/ethernet_frame_padding_synthesis.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

Same error if I do not specify -DFNS_ROCE_STACK_MAX_QPS=500
How to fix this error?

Your fields mask for the computation of the ICRC is wrong.
I believe that the ICRC masked fields these are related to the RoCEv1 specification [1]. In fact here we can find the masked field for the GRH (traffic class, flow label and hop limit).
RoCEv2 ICRC specification can be found here [2].

The computation itself cannot run at 100 Gbps, in fact the unrolled loop cannot be pipelined efficiently, implementing the RoCEv2 IP with the ICRC enabled will cause a WNS of ~60 ns (10 times the clock period).

[1] InfiniBand Architecture Specification Volume 1 Release 1.4 Pg. 1913 (RoCEv1), Pg. 218 (Infiniband ICRC)
[2] InfiniBand Architecture Specification Volume 1 Release 1.4 Pg. 1935-1936

I have added timing constraint as following:
dclock=8ns
refclock=6.4ns.

Then i run synthesis and Report Timing Summary. I have observed following :
Setup:

Worst Negative Slack: -5.6ns

Hold:

Worst Hold Slack=-0.349ns

Pulse Width:

Worst Pulse Width Slack= -0.02ns

My understanding is that all above values should be positive for meeting timing constraint before running on hardware.
I do not have hardware VCU118 now but i will get in future. I want to make sure that design work on real hardware without any surprises.

Please comments/suggest.

Thanks and regards,
Ishtiyaque
[email protected]

The "make installip" failed saying there's no valid part for the project.
CentOS 7 + Vivado 2019.2

Here's my procedure:
1. mkdir build (successful)
2. cd build (successful)
3. cmake .. -DDEVICE_NAME=vcu118 (successful)
4. make installip (failed)

And it errors out with message:
source /program/Xilinx/Vivado/2019.2/scripts/vivado_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/program/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'xlab' on host 'localhost' (Linux_x86_64 version 3.10.0-1062.4.3.el7.x86_64) on Tue Nov 26 03:56:57 CST 2019
INFO: [HLS 200-10] On os "CentOS Linux release 7.7.1908 (Core)"
INFO: [HLS 200-10] In directory '/home/xlab/Documents/toe/build/hls/ethernet_frame_padding'
Sourcing Tcl script 'make.tcl'
INFO: [HLS 200-10] Opening project '/home/xlab/Documents/toe/build/hls/ethernet_frame_padding/ethernet_frame_padding_prj'.
INFO: [HLS 200-10] Opening solution '/home/xlab/Documents/toe/build/hls/ethernet_frame_padding/ethernet_frame_padding_prj/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.2ns.
INFO: [HLS 200-10] Setting target device to 'xcvu9p-flga2104-2L-e'
INFO: [HLS 200-10] Adding design file '/home/xlab/Documents/toe/hls/ethernet_frame_padding/ethernet_frame_padding.cpp' to the project
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2019.2 (64-bit)
**** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
**** IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
ERROR: [Project 1-848] Could not get a valid part for the project. Make sure you have the required part installed, use the get_parts command to see the list of valid parts.
INFO: [Common 17-206] Exiting Vivado at Tue Nov 26 03:57:09 2019...
ERROR: [IMPL 213-28] Failed to generate IP.

We have loaded bit stream for TOE project on VCU118. ethernet_10g_ip is transmitting packet which can capture through the tcpdump on network. However when we tried to ping we do not see any activity on rx side of the ethernet_10g_ip. I have captured stat_rx_local_fault and stat_rx_internal_local_fault of ethernet_10g_ip using ILA. These stats are coming continuously high.

I will appreciate if we can get pointer to debug this issue further.

thanks and regards,
Ishtiyaque Shaikh

Hi Dsidler,
I use the code you have provided to create a project for a test on board vcu118 . After download the bit , the Ehernet was linked up ,but when I use the ping test :ping 10.1.212.209,it was failed. So I try to use the chipscope to debug,and I found that the network_module have received the ARP request message ,and transferred to the network_stack module, it seems that the arp_server_subnet_ip module dropped the ARP message and it haven't reply a ARP response message.
Do you have any suggestions? thank you !

Hi guys, your project is great.
I know this question is rhetorical but I’m trying to get started with a VCU 707 board and was wondering if your code is extendable to the Xilinx’ VCU 707 board?

Thanks

I've been trying to generate the bitstream targeting VCU118 for benchmark purposes.

To generate the bitstream, the wiki says to run Vivado using create_vcu118_proj.tcl, which is now located in scripts instead of projects.

Even after manually modifying the script to satisfy the current repository (redirecting rtl to hdl, upgrading IP versions, etc.) the build outputs error at the following step:

# update_compile_order -fileset sources_1
# create_ip -name ip_handler -vendor ethz.systems -library hls -version 1.2 -module_name ip_handler_ip -dir $ip_dir/vu9p
ERROR: [Coretcl 2-1134] No IP matching VLNV 'ethz.systems:hls:ip_handler:1.2' was found. Please check your repository configuration.

It would be most helpful if there was an up-to-date method detailing how to generate the bitstream.

Hi,
I have followed process for generating bit stream for VCU118. I got evaulation license for ethernet_10g_ip from xilinx. As per my network configuration i haved changed mac adress, ip address and default gateway in tcp_ip_top.v/network_module.v
After all above changes i am not able to ping the board. I have put ILA and try to see if some activity is showing on parallel RX/TX interface of mac. If i start udp iperf client i can see packet coming on parallel TX interface of MAC but it is not coming out of board . I have run tcpdump on iperf server but no activity. The most basic ping is also not coming on parallel RX interface. Can anyone suggest way to debug further ?

regards,
Ishtiyaque Shaikh

Hi, expert:
Is it possibel to support xilinx kc705 or kcu105 board?

Bug situation: In my test, the APP established multiple connections through the TCP interface. When retransmission and address loopback occur, the retransmission data is abnormal.
Expected behavior: When retransmission and address wrapping occur at the same time, TCP should issue two read commands to DDR. The start address of the second read command should be {SESSION_ID,{WINDOW_BITS{1’b0}}.
Actual behavior: According to line 1489 of the txEngMemAccessBreakdown() module in hls/toe/tx_engine/tx_engine.cpp, the start address for the second read command is incorrectly set to 0.
outputMemAccess.write(mmCmd(0, cmd.bbt - lengthFirstAccess));
Possible modifications:

ap_uint<32> pkgAddr;
pkgAddr(31, 30) = cmd.saddr(31, 30);
pkgAddr(29, WINDOW_BITS) = cmd.saddr(29, WINDOW_BITS);
pkgAddr(WINDOW_BITS-1, 0) = 0;
outputMemAccess.write(mmCmd(pkgAddr, cmd.bbt - lengthFirstAccess));

wrong # args: should be "file mkdir name ?name ...?"
while executing
"file mkdir "
invoked from within
"if {$command == "synthesis"} {
csynth_design
} elseif {$command == "csim"} {
csim_design -clean -argv {0 /home/sky/work/fpga_net_stack/fpga-netw..."
(file "make.tcl" line 39)
invoked from within
"source make.tcl"
("uplevel" body line 1)
invoked from within
"uplevel #0 [list source $arg] "

INFO: [Common 17-206] Exiting vivado_hls at Fri Mar 29 11:28:31 2024...
make[3]: *** [CMakeFiles/installip.toe.dir/build.make:76: CMakeFiles/installip.toe] Error 1
make[2]: *** [CMakeFiles/Makefile2:110: CMakeFiles/installip.toe.dir/all] Error 2
make[1]: *** [CMakeFiles/Makefile2:90: CMakeFiles/installip.dir/rule] Error 2
make: *** [Makefile:118: installip] Error 2

Hi,
We were able to synthesize the fpga network stack code. But when we tried to do the CSimulation, we found compile issues with toe_tb.cpp, toe.cpp and toe.hpp. We have concern that if this code is recently tested and have complete implementation. Has anyone tested generated bitstream on vc709 successfully ?

thanks and regards,
Ishtiyaque

Hi David, can you also please provide the test vectors for the RoCE module (or the corresponding scripts to generate such test vectors)?
In the script they should be

write_read_read_large_receiver.in
write_read_read_large_receiver.out
rdma_txwriteread.in
rdma_txwriteread.out

Thank you very much!

Hi, Sidler~

I see the module "hls/toe" cannot be synthesized by HLS, and the build progress errors out with messages like this:~

ERROR: [HLS 200-70] Compilation errors found: In file included from ../../../hls/toe/ack_delay/ack_delay.cpp:1:
In file included from ../../../hls/toe/ack_delay/ack_delay.cpp:30:
In file included from ../../../hls/toe/ack_delay/ack_delay.hpp:29:
In file included from ../../../hls/toe/ack_delay/../toe_internals.hpp:4:
In file included from ../../../hls/toe/ack_delay/../../axi_utils.hpp:32:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\iostream:39:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\ostream:39:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\ios:39:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\exception:151:
D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\exception_ptr.h:132:13: error: unknown type name 'type_info'
      const type_info*
            ^
In file included from ../../../hls/toe/ack_delay/ack_delay.cpp:1:
In file included from ../../../hls/toe/ack_delay/ack_delay.cpp:30:
In file included from ../../../hls/toe/ack_delay/ack_delay.hpp:29:
In file included from ../../../hls/toe/ack_delay/../toe_internals.hpp:4:
In file included from ../../../hls/toe/ack_delay/../../axi_utils.hpp:32:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\iostream:39:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\ostream:39:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\ios:39:
In file included from D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\exception:151:
D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\nested_exception.h:62:5: error: the parameter for this explicitly-defaulted copy constructor is const, but a member or base requires it to be non-const
    nested_exception(const nested_exception&) = default;
    ^
D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\nested_exception.h:64:23: error: the parameter for this explicitly-defaulted copy assignment operator is const, but a member or base requires it to be non-const
    nested_exception& operator=(const nested_exception&) = default;
                      ^
D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\nested_exception.h:77:28: error: exception specification in declaration does not match previous declaration
  inline nested_exception::~nested_exception() = default;
                           ^
D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\nested_exception.h:66:20: note: previous declaration is here
    inline virtual ~nested_exception();
                   ^
D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\nested_exception.h:122:61: error: redefinition of default argument
    __throw_with_nested(_Ex&& __ex, const nested_exception* = 0)
                                                            ^ ~
D:/Xilinx/Vivado/2019.2/win64/tools/clang/bin\..\lib\clang\3.1/../../../include/c++/4.5.2\nested_exception.h:110:56: note: previous definition is here
    __throw_with_nested(_Ex&&, const nested_exception* = 0)
                                                       ^ ~
5 errors generated.

I tried to open the cmake-generated project with HLS GUI, and this error is confirmed.

Windows 7.1 + Vivado 2019.2 + MinGW 16.1 + CMake 3.15

Please help to double check with this.

Best Regards :- )
[email protected]

I was trying to do the make and it complained about the create_project.tcl:
CMake Error: File /home/fpga-network-stack/projects/create_project.tcl.in does not exist.
CMake Error at CMakeLists.txt:97
Line 97 of the CMakeLists.txt is looking for projects, I think it should be scritps .

Thanks.

Hi,

I am currently reading the code of your network stack and want to port it to a Zynq 7100 board. Even though I have huge troubles building a complete project for one of the example boards, I think I got how most of this stuff works and I'm trying to build a Vivado block diagram to get some simple ARP, and ICMP going for now to iterate on with UDP and later TCP.

However, I don't know why there are AXI4-Stream register slices between a bunch of the cores. I don't see a clock domain crossing and as far as I can see, the slices don't contain any FIFOs, right? Could you please elaborate why the slices are necessary?

Thanks,

• Andy