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1000base-x

1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)

100g-fpga-network-stack-core

This repo contains the Limago code

10base_t_software_phy

1g_cml_openflow

OpenFlow switch for NetFPGA 1G CML

8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

adapter

An FPGA-based NetTLP adapter

aes-fpga

AES加密解密算法的Verilog实现

aes-over-pcie

A VHDL implementation of 128 bit AES encryption with a PCIe interface.

aes_netfpga10g

Design and implementation of the AES crypto authentication module based on NetFPGA10G card

ahci_mpi

an sata controller using smallest resource.

antikernel-ipcores

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

archlab2015

2015秋季学期组成原理实验 & 2013级系统方向综合实验 - NPC

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

atmega8_bootloader

awesome-dv

Awesome ASIC design verification

awesome-fpga

A collection of resources on FPGA devices and development in general

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

ax4010

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

axi-lite-slave

Slaves for AXI-lite interface

axis-async-fifo

parameterized AXIS FIFO design

basic_verilog

Must-have verilog systemverilog modules

bfd_artix

bluespecpcie

PCIe library for the Xilinx 7 series FPGAs in the Bluespec language

boolking.github.io

blog

bsc

Bluespec Compiler (BSC)

butterflylogic

cdpga

FPGA core boards / evaluation boards based on CDCTL hardware

chips-2.0

FPGA Design Suite based on C to Verilog design flow.

cocotb

Coroutine Co-simulation Test Bench