fischermoseley / manta Goto Github PK

Right now each Ethernet packet is a single bus transaction, which is rather inefficient as multiple bus transactions can easily be packed into the data field of an Ethernet packet. Some thought should go into making sure that packets are generated at the right time - bytes can be sent at any time with UART, but since Ethernet has a bunch of headers the timing problem is a little more complicated.

Right now the block_memory module implements an arbitrarily sized block memory as $N$ 16-bit BRAMs in parallel. This is totally fine, but these are mapped into Manta's internal memory space such that the entires are interleaved - which requires a few modulo and division operators that totally wreck the timing performance when large inputs are used.

Instead of interleaving each core's address space, Manta could just place each 16-bit wide BRAM in address space sequentially.

As an example, a 34-bit wide BRAM would presently be mapped onto Manta's internal bus as:

Instead, it could be mapped as:

And this would swap out the modulo (and division) operations on the FPGA for a simple 'is this address in memory bounds' check, which is just a comparision.

Hello! Thank you for working on and releasing Manta, very excited to use it more and see where it goes!

This evening I was trying to use the logic analyzer core for the first time, but I'm running into errors when I try to grab a capture from it.

>>> manta.logic_analyzer.capture()
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "/home/kwilke/.local/lib/python3.10/site-packages/manta/logic_analyzer/__init__.py", line 249, in capture
    raw_capture = self._sample_mem.read(addrs)
  File "/home/kwilke/.local/lib/python3.10/site-packages/manta/memory_core.py", line 264, in read
    datas = self._interface.read(bus_addrs)
  File "/home/kwilke/.local/lib/python3.10/site-packages/manta/uart/__init__.py", line 174, in read
    raise ValueError(
ValueError: Only got 133 out of 1792 bytes.

I'm not sure yet what's the issue is, my test device is a pico-ice board and I'm putting my work into this repo: https://github.com/KennethWilke/ti-linkeroo/tree/6b7c76d6c55076a3bd039c31b04d333e93ee1e76

My manta.yaml contains:

---
cores:
  io_pins:
    type: io

    inputs:
      sw2: 1

    outputs:
      r: 1
      g: 1
      b: 1

  logic_analyzer:
    type: logic_analyzer
    sample_depth: 4096
    trigger_location: 1

    probes:
      tip: 1
      ring: 1

    triggers:
      - tip FALLING
      - ring FALLING

uart:
  port: "/dev/ttyACM1"
  baudrate: 115_200
  clock_freq: 12_000_000

I took a little break then set everything back up again, and now the behavior is a little better but still running into similar read errors, I also attached my flipper zero to the tx pin of my pico so I could watch the data streaming back. What I see now is: I trigger the capture via python, then the pico begins to stream back packets like D0002, then when I cause one of my probe pins to fall the trigger hits and I get this error back on the Python side:

>>> manta.logic_analyzer.capture()
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "/home/kwilke/.local/lib/python3.10/site-packages/manta/logic_analyzer/__init__.py", line 249, in capture
    raw_capture = self._sample_mem.read(addrs)
  File "/home/kwilke/.local/lib/python3.10/site-packages/manta/memory_core.py", line 264, in read
    datas = self._interface.read(bus_addrs)
  File "/home/kwilke/.local/lib/python3.10/site-packages/manta/uart/__init__.py", line 174, in read
    raise ValueError(
ValueError: Only got 126 out of 1792 bytes.

If I try 2 more times to perform the capture, I'll get errors like: ValueError: Logic analyzer did not reset to IDLE state. then on the 3rd re-attempt it looks like the analyzer gets back into a good waiting condition until I cause the trigger to fire.

The IO core that's running in the same design seems to be working okay, if I perform a manta.io_pins.set_probe("b", 1) my blue LED lights up. Though, immediately after triggering the above ValueError the first io command I send is ignored, but after that it works. Hopefully that's some kind of clue too 😅

I've had different quantity byte lengths returned for this error too, it's usually 126 but sometimes its 119 or 133 and on at least 1 occasion it was 98. Sometimes after I hit the capture error, when I would try a writing io command I would get what looks like 5 more D0002 packets back that I suspect was a buffered response from the attempted capture. I see these flow through my flipper zero to after I send the io command, so I think it's buffered on the device somewhere

I'll continue to tinker to see what I find, I keep wondering if my slow UART is going to be a problem here.

Right now they're packed, which simplifies the Verilog a little bit but ends up making them incompatible with Yosys and the Icestick toolchain.

This isn't necessarily hard - but it's worth thinking about how signals should be formatted. For instance, if I've got a logic analyzer with a config of:

---
cores:
  my_logic_analyzer:
    type: logic_analyzer
    sample_depth: 4096
    trigger_loc: 1000

    probes:
      probe0: 1
      probe1: 2

    triggers:
      - probe0 RISING

Then does it make sense to look at the capture data as:

>>> data = my_logic_analyzer.capture()
>>> data.probe0
[sample_0, sample_1, sample_2...]
>>> data.trigger_location
1024

Or does another mechanism make sense?

At one point I swapped out the Logic Analzyer core for a simpler version, but some features are missing that should be readded:

• CDC is currently not being performed
• The FSM does not currently respect capture modes
• External triggers are currently not supported
• The trigger block only supports global OR, not AND

All of these should be probably be taken care of at once, hence why they're all in one issue.

Right now it's only advertised in the repo structure page, and there's not any instructions for how to build them. It really is just as simple as setting a few environment variables and running the build.sh script, but I think that could be advertised a bit better.

I've got one lying around, and I think it'd be useful to provide some examples with the Gigabit Ethernet that's on the Nexys Video. And if I can toss in a HDMI source then it should be possible to demonstrate network video streaming - which would be a lovely display of the bandwidth you can get with Manta over Ethernet.

This should remove a somewhat large dependency for folks using Ethernet, but some care will need to go into making sure cross-platform behavior is consistent. Scapy has a ton of functionality, but Manta only uses it to send L2 packets and would likely be better served by the builtin library.

At one point I swapped out the IO core for a simpler version to dodge some bugs, but that removed some features that should be reimplemented. In particular:

• Probes with widths >16 bits should be re-added.
• CDC is currently not being performed.
• The strobe register is presently not in use.

All of these should be probably be taken care of at once, hence why they're all in one issue.

It's worth noting that one can workaround the 16-bit width constraint by making multiple probes and concatenating them together. That's probably the best way to handle this within Manta's Verilog honestly.

This seems like a really cool project which I'm excited to use, but unfortunately, it doesn't seem to work very well with yosys, at least targeting ECP5s.

First, there are some compilation errors in the block_memory module

The type casts here aren't supported

    localparam N_BRAMS = int'($ceil(real'(WIDTH) / 16.0));

and neither are these multi-dim arrays.

    reg [N_BRAMS-1:0][ADDR_WIDTH-1:0] addra = 0;
    reg [N_BRAMS-1:0][15:0] dina = 0;

There may be others, but I looked to other methods at this point, in particular running through https://github.com/zachjs/sv2v takes care of most of these, but the real cast is still a problem.

With sv2v and some manual intervention in the N_BRAMS computation I was able to get it to compile, but yosys seems to fail to map the BRAM to BRAMs. I can't see an obvious reason for that :/

Edit: The config I used

---
cores:
  my_logic_analyzer:
    type: logic_analyzer
    sample_depth: 4096
    trigger_loc: 1000

    probes:
      lp_detect: 1
      dbg_raw_ddr: 2
      dbg_raw_deser: 16
      dbg_aligned: 16
      dbg_aligned_valid: 2
      dbg_wait_sync: 2

    triggers:
      - moe FALLING

uart:
  port: "auto"
  baudrate: 115200
  clock_freq: 100000000

On windows.

apio (yosys, nextpnr, icepack, iceprog) builds and uploads the code without complaint

I have tried both logic analyzer and io and get the same result

ValueError: Only got 0 out of 7 bytes.

fpga is alchrity cu - 100mhz ice 40 board

I know its the correct , working com port because if I load some code to the board that uses the port and open a serial terminal connection to the board :-

• works fine (my code that is)
• manta complains that it cannot open the port because its in use

(Note that the code I am using with manta is not using the serial port, I used different code to verify that the serial port works correctly)

config file

cores:
  my_io_core:
    type: io

    inputs:
      val0: 4

  my_logic_analyzer:
    type: logic_analyzer
    sample_depth: 4096
    trigger_location: 1000

    probes:
      value: 4
      sw0: 1
    triggers:
      - sw0 RISING

uart:
  port: "COM6"
  baudrate: 115200
  clock_freq: 100_000_000

reading val0 gives

>>> manta.my_io_core.get_probe("val0")
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Lib\site-packages\manta\io_core.py", line 233, in get_probe
    datas = self._interface.read(probe["addrs"])
            ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Lib\site-packages\manta\uart\__init__.py", line 174, in read
    raise ValueError(
ValueError: Only got 0 out of 7 bytes.
>>>

same fail stack with logic analyzer

PS C:\work\alchrity_cu\io_tests> manta capture manta.yaml my_logic_analyzer capture.vcd top.v
Traceback (most recent call last):
  File "<frozen runpy>", line 198, in _run_module_as_main
  File "<frozen runpy>", line 88, in _run_code
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Scripts\manta.exe\__main__.py", line 7, in <module>
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Lib\site-packages\manta\cli.py", line 151, in main
    capture(argv[2], argv[3], argv[4:])
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Lib\site-packages\manta\cli.py", line 95, in capture
    cap = la.capture()
          ^^^^^^^^^^^^
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Lib\site-packages\manta\logic_analyzer\__init__.py", line 197, in capture
    state = self._fsm.registers.get_probe("state")
            ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Lib\site-packages\manta\io_core.py", line 233, in get_probe
    datas = self._interface.read(probe["addrs"])
            ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "C:\Users\paulm\AppData\Local\Programs\Python\Python312\Lib\site-packages\manta\uart\__init__.py", line 174, in read
    raise ValueError(
ValueError: Only got 0 out of 7 bytes.