Related Issues (12)
- Switch from Scapy to builtin Python sockets library
- Yosys-compatible verilog HOT 2
- Not enough bytes received during Logic Analyzer capture HOT 12
- help with 'Only got 0 out of 7 bytes' HOT 2
- Port examples to the Nexys Video
- Reference examples in documentation site
- Add method for dumping logic analyzer contents to Python
- Convert block_memory address/data/write enable arrays to unpacked
- Refactor block_memory addressing scheme to not use modulo operator
- Re-add some IO core features
- Re-add some Logic Analyzer core features
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