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Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.

Home Page: https://www.emb4fun.de/riscv.html

Batchfile 0.08% Mathematica 0.08% VHDL 33.73% JavaScript 0.39% Assembly 1.62% C 24.95% Tcl 1.64% Verilog 10.00% SystemVerilog 25.02% HTML 0.91% Fortran 0.01% Shell 0.57% Python 0.07% Makefile 0.84% C++ 0.10%

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neorv32-examples's Issues

Mate from "neorv32-complex-setups" needs a bit support

Hello, we meet each other in a conversation of NeoRV32 Pull request, stnolting/neorv32#194
I started a new repository for the ULX3S SDRAM setup: https://github.com/zipotron/neorv32-complex-setups
I am basing my job in your work and Lawrie's ULX3S SDRAM controller https://github.com/zipotron/sdram-fpga
My last steps for the integration of the SDRAM controller with the Wishbone of NeoRV32 are in https://github.com/zipotron/neorv32-complex-setups/tree/wiring_sdram
But I got stack, I am using the Open-source toolchain (that is sometimes a big headache) and I am getting a completely non-descriptive error:

ERROR: cell type 'wb_sdram' is unsupported (instantiated as 'inst_wb_sdram')

I had review how I was wiring everything, but seams all OK, I have no idea about what can be the cause of this, I would really appreciate if you (that already did a success integration) have a fast look and give me any kind of advice.
In advance, thanks a lot!

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