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View Code? Open in Web Editor NEWSome neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.
Home Page: https://www.emb4fun.de/riscv.html
Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.
Home Page: https://www.emb4fun.de/riscv.html
Hello, we meet each other in a conversation of NeoRV32 Pull request, stnolting/neorv32#194
I started a new repository for the ULX3S SDRAM setup: https://github.com/zipotron/neorv32-complex-setups
I am basing my job in your work and Lawrie's ULX3S SDRAM controller https://github.com/zipotron/sdram-fpga
My last steps for the integration of the SDRAM controller with the Wishbone of NeoRV32 are in https://github.com/zipotron/neorv32-complex-setups/tree/wiring_sdram
But I got stack, I am using the Open-source toolchain (that is sometimes a big headache) and I am getting a completely non-descriptive error:
ERROR: cell type 'wb_sdram' is unsupported (instantiated as 'inst_wb_sdram')
I had review how I was wiring everything, but seams all OK, I have no idea about what can be the cause of this, I would really appreciate if you (that already did a success integration) have a fast look and give me any kind of advice.
In advance, thanks a lot!
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