digilent / arty Goto Github PK

The system wrapper for the generated project does not automatically update when making port level changes. You must delete it and re-create an HDL wrapper to update it

create_root_design ""

ERROR: [IP_Flow 19-3461] Value 'shield_dp0_dp19' is out of the range for parameter 'GPIO BOARD INTERFACE(GPIO_BOARD_INTERFACE)' for BD Cell '/axi_gpio_0' . Valid values are - Custom, dip_switches_4bits, i2c_pullups, led_4bits, push_buttons_4bits, rgb_led
INFO: [IP_Flow 19-3438] Customization errors found on '/axi_gpio_0'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

while executing

"rdi::add_properties -dict {CONFIG.C_GPIO_WIDTH 20 CONFIG.C_INTERRUPT_PRESENT 1 CONFIG.GPIO_BOARD_INTERFACE shield_dp0_dp19 CONFIG.USE_BOARD_FLOW true}..."
invoked from within
"set_property -dict [ list CONFIG.C_GPIO_WIDTH {20} CONFIG.C_INTERRUPT_PRESENT {1} CONFIG.GPIO_BOARD_INTERFACE {shield_dp0_dp19} CONFIG.USE_BOARD_F..."
(procedure "create_root_design" line 71)
invoked from within
"create_root_design """
(file "../src/bd/system.tcl" line 898)

while executing

"source $origin_dir/src/bd/system.tcl"
(file "./create_project.tcl" line 103)

Hi, the following properties are missing from Arty's XDC which causes a lot of warnings to be generated:

## Voltage config
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

Hi,

I am wondering if the published files are under any license that allows redistribution.

Best,
Stefan

The correct numbering must be

#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; 
#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }];
#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; 
#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; 
#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; 
#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { jb[8] }]; 
#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { jb[9] }]; 
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[10] }]; 

wrong .xdc file in https://github.com/Digilent/Arty/blob/master/Projects/XADC_Demo/src/constraints/Arty_Master.xdc