You mention that this is the instruction for adding 64-bit integers. From the RISC-V spec this opcode is only for 32-bit integers.

Hello, I compiled the xv6 kernel myself and find the compiler uses the C extension of riscv, so the emulator failed to run the binary.
How did you modify the makefile of xv6 to disable the C extension?

Excuse me ,I am a new hand, and the particularity of SIE confuses me a lot.
Could me tell me why read/write SIE register is different from other register?

    /// Load a value from a CSR.
    pub fn load_csr(&self, addr: usize) -> u64 {
        match addr {
            SIE => self.csrs[MIE] & self.csrs[MIDELEG],
            _ => self.csrs[addr],
        }
    }

    /// Store a value to a CSR.
    pub fn store_csr(&mut self, addr: usize, value: u64) {
        match addr {
            SIE => {
                self.csrs[MIE] =
                    (self.csrs[MIE] & !self.csrs[MIDELEG]) | (value & self.csrs[MIDELEG]);
            }
            _ => self.csrs[addr] = value,
        }
    }

Thanks for your kindness. You have written such a tutorial and shared your code, which encourages me to learn it and complete the tutorial.

The new project is available at here and the online book is hosted on github page.

I have used most of your code and follow the structure of yours. I hope this tutorial will be helpful for anyone who want to learn about RISC-V emulator.

hey, d0iasm,
your project rvemu is awesome and makes me excting! but the rvemu for book seems not to be finished, i really look forworad your book! Hope to see it soon!

The section explaining why rvemu is little-endian may mislead readers because it is not precise enough.

While the base memory system does not need to be little-endian with regards to instruction decoding, the current standardized memory operations do have to be little-endian. I think this may have been a requirement added after the 1.0 release of the specification, but I don't want to track down when it was added.

From: https://book.rvemu.app/setup-and-implement-two-instructions

RISC-V has either little-endian or big-endian byte order, but our emulator will implement a little-endian system since it is currently dominant commercially like x86 systems.

Section 1.2 of RISC-V Specification v2.0

The base RISC-V ISA has a little-endian memory system, but non-standard variants can provide a big-endian or bi-endian memory system

The section goes on to explain the exact (rather complex) memory requirements of the RISC-V.

Section 2.6 of RISC-V Specification v2.0

RV32I provides a 32-bit user address space that is byte-addressed and little-endian.