crossroadsfpga / pigasus Goto Github PK

100Gbps Intrusion Detection and Prevention System

Tcl 2.48% Mathematica 0.01% Shell 0.41% SystemVerilog 17.12% Python 1.11% CMake 0.81% C 2.50% Ruby 0.01% HTML 6.30% Lua 1.00% C++ 67.89% Makefile 0.01% Batchfile 0.01% Verilog 0.33%

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Can't Find Ports in top.sv when Generating Bitstream

Coming across this issue on both 19.3 and 20.1 with updated components when generating the bitstream.
This is when I'm running "./run_quartus_synth.sh"
Error shown in image below.

Could not get kernel memory

Hi,
Thank for your work.
I'm trying to run Pigasus with our Stratix MX board. I'm able to flash FPGA bit stream, the host recognized the FPGA device as

uname -a
Linux mx 4.15.0-180-generic #189-Ubuntu SMP Wed May 18 14:13:57 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux

# output of dmesg

##################################################
# After reboot machine
##################################################
....
[    3.465425] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
[    3.465425] lpc_ich: Resource conflict(s) found affecting gpio_ich
[    3.469691] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[    3.620181] FPGA manager framework
[    3.641212] altera-cvp 0000:01:00.0: Wrong EXT_CAP_ID value 0x0
.....
##################################################
# After insert driver
##################################################
[  227.021978] intel_fpga_pcie_drv: loading out-of-tree module taints kernel.
[  227.022004] intel_fpga_pcie_drv: module verification failed: signature and/or required key missing - tainting kernel
[  227.022360] Mapping BAR: 0
[  227.022378] Mapping BAR: 1
[  227.022379] Mapping BAR: 2
[  227.022386] Mapping BAR: 3
[  227.022387] Mapping BAR: 4
[  227.022387] Mapping BAR: 5

Howerver, when running Pigagus, I got Could not get kernel memory message

pigasus -c snort.lua --patterns ./rule_list
--------------------------------------------------
o")~   Snort++ 3.0.0-249
--------------------------------------------------
Loading snort.lua:
        ssh
        pop
        reject
        stream_tcp
        dce_http_proxy
        normalizer
        stream_udp
        search_engine
        dce_smb
        ips
        binder
        detection
        modbus
        network
        sip
        ssl
        dce_http_server
        dce_tcp
        smtp
        ftp_data
        ftp_server
        telnet
        rpc_decode
        http_inspect
        classifications
        stream
        stream_ip
        process
        profiler
        event_queue
        dnp3
        active
        ftp_client
        references
        dns
        dce_udp
        imap
Finished snort.lua.
Loading rules:
Loading ../rules/sample.rules:
Finished ../rules/sample.rules.
Finished rules.
--------------------------------------------------
rule counts
       total rules loaded: 1
               text rules: 1
            option chains: 1
            chain headers: 1
--------------------------------------------------
port rule counts
             tcp     udp    icmp      ip
     any       1       0       0       0
   total       1       0       0       0
Creating Port Groups....

IP-SRC 0 Port Groups in Port Table

IP-DST 0 Port Groups in Port Table

IP-ANY  PortObject any  Id:0  Ports:1 Rules:0
 {
 Ports [any ]
 }
PortGroup rule summary (ports):

ICMP-SRC 0 Port Groups in Port Table

ICMP-DST 0 Port Groups in Port Table

ICMP-ANY  PortObject any  Id:0  Ports:1 Rules:0
 {
 Ports [any ]
 }
PortGroup rule summary (ports):

TCP-SRC 0 Port Groups in Port Table

TCP-DST 0 Port Groups in Port Table

TCP-ANY  PortObject any  Id:0  Ports:1 Rules:1
 {
 Ports [any ]
 }
init mpse: hyperscan
FP port 1:60200:1 packet[6] = '....".' |FA A5 F8 FB 22 88 | ( user )
PortGroup rule summary (ports):
        packet: 1

UDP-SRC 0 Port Groups in Port Table

UDP-DST 0 Port Groups in Port Table

UDP-ANY  PortObject any  Id:0  Ports:1 Rules:0
 {
 Ports [any ]
 }
PortGroup rule summary (ports):

SVC-ANY  PortObject any  Id:0  Ports:1 Rules:0
 {
 Ports [any ]
 }
PortGroup rule summary (ports):
Port Groups Done....
Creating Rule Maps....
Rule Maps Done....
Creating Service Based Rule Maps....
+--------------------------------
| Service-PortGroup Table Summary 
---------------------------------
---------------------------------
Service Based Rule Maps Done....
--------------------------------------------------
fast pattern port groups        src     dst     any
                   packet:        0       0       1
--------------------------------------------------
search engine
                instances: 1
                 patterns: 1
init mpse: hyperscan
init mpse: hyperscan
init mpse: hyperscan
init mpse: hyperscan
init mpse: hyperscan
init mpse: hyperscan
init mpse: hyperscan
--------------------------------------------------
pcap DAQ configured to passive.
Commencing packet processing
elapsed = 3400402671 
clock scale = 3400 
usec 1000118.437500 
Core_id:0
Could not get kernel memory!
nb matches: 0
nb no matches: 0
--------------------------------------------------
Packet Statistics
--------------------------------------------------
Module Statistics
--------------------------------------------------
Summary Statistics
--------------------------------------------------
timing
                  runtime: 00:00:02
                  seconds: 2.987
                  packets: 0
                 pkts/sec: 0
o")~   Snort exiting

I added few printk messages and found that the address is 0

# dmesg
[ 2141.817004] set_kmem_size
[ 2141.817005] dev_bk->kmem_info.size=0
[ 2141.817006] dev_bk->kmem_info.virt_addr=0
[ 2141.817006] dev_bk->kmem_info.bus_addr=0
[ 2141.817091] dev_bk->kmem_info.virt_addr=0
[ 2141.817092] could not allocate 2
[ 2141.817092] Core_id:0

Could you please give few hints on what would be wrong/missing steps?

Thank you!

Regenerate the memory init file

Hi,

I'm trying to integrate pigasus to our IPS equipment,but rule file is a little different.How can I regenerate the memory init file?
I read the doc and src in the project, but I couldn't find it.

Thanks
^^

Running Pigasus Issues

1) Error when inserting the kernel module.

randy@agent40:~/pigasus/software/src/pigasus/pcie/kernel/linux$ sudo ./install
make -C /lib/modules/5.11.0-25-generic/build M=/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux clean
make[1]: Entering directory '/usr/src/linux-headers-5.11.0-25-generic'
make[1]: Leaving directory '/usr/src/linux-headers-5.11.0-25-generic'
make -C /lib/modules/5.11.0-25-generic/build M=/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux modules
make[1]: Entering directory '/usr/src/linux-headers-5.11.0-25-generic'
  CC [M]  /home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_chr.o
  CC [M]  /home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.o
/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.c: In function ‘intel_fpga_pcie_dma_send’:
/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.c:133:20: error: storage size of ‘start_tv’ isn’t known
  133 |     struct timeval start_tv, end_tv;
      |                    ^~~~~~~~
/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.c:133:30: error: storage size of ‘end_tv’ isn’t known
  133 |     struct timeval start_tv, end_tv;
      |                              ^~~~~~
/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.c:171:5: error: implicit declaration of function ‘do_gettimeofday’; did you mean ‘do_settimeofday64’? [-Werror=implicit-function-declaration]
  171 |     do_gettimeofday(&start_tv);
      |     ^~~~~~~~~~~~~~~
      |     do_settimeofday64
/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.c:133:30: warning: unused variable ‘end_tv’ [-Wunused-variable]
  133 |     struct timeval start_tv, end_tv;
      |                              ^~~~~~
/home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.c:133:20: warning: unused variable ‘start_tv’ [-Wunused-variable]
  133 |     struct timeval start_tv, end_tv;
      |                    ^~~~~~~~
cc1: some warnings being treated as errors
make[2]: *** [scripts/Makefile.build:287: /home/randy/pigasus/software/src/pigasus/pcie/kernel/linux/intel_fpga_pcie_dma.o] Error 1
make[1]: *** [Makefile:1848: /home/randy/pigasus/software/src/pigasus/pcie/kernel/linux] Error 2
make[1]: Leaving directory '/usr/src/linux-headers-5.11.0-25-generic'
make: *** [Makefile:17: all] Error 2
Loading module
insmod: ERROR: could not load module ./intel_fpga_pcie_drv.ko: No such file or directory

2) Reading back received and processed packets

This is how I program the chip through the programmer GUI,

I then send ARPs from our packet generator using osmode on our Napatech board which has both ports connected directly to the Pigasus board. In the JTAG system console I test all three JTAG options and do not see any packets other than 1 coming in and being processed by the Pigasus board.

No such file config_changes.txt

When running command "make -j $(nproc) install", I get the following warning. When line 110 is commented out frompigasus/software/build_pigasus/doc/cmake_install.cmake it works fine. Is there something I missed in the prior steps for not having config_changes.txt?

graphviz

Hi,
graphviz is available, however following error occurs, does anyone have BKM?

$ sudo python3 pigasus.py 
Traceback (most recent call last):
  File "pigasus.py", line 19, in <module>
    from fluid.visualizer import *
  File "/home/kobu/kobuworks/pigasus/fluid/visualizer.py", line 1, in <module>
    from graphviz import Graph, Digraph
ModuleNotFoundError: No module named 'graphviz'

thanks,
BR/Kobu

./run_ipgen.sh failed

Hi,

When I tried to run the script run_ipgen.sh, I found out that this script failed, and showed the following errors in the log:

and finally it was killed directly

I wonder whether I have missed some components that are required by Pigasus? I am using Ubuntu 20.04 VM, and I have already installed Quartus Pro 19.3 and set the required environment variables.

I also tried to run the vsim directly after that, but it seems that some IP core are not available:

I really appreciate it if someone could help me, since Pigasus 2.0 is promising and easy to use.

Thanks,
Junzhi

Use Intel XL710 for 40GbE QSFP

Hi @hsadok
I have single PC with both Stratix MX board and XL710 for 40GbE QSFP (both Pigasus and Pktgen will be run on the same machine. The Stratix MX and X710 NICs are connected together).

The Pigasus is starting OK. However when I start pktgen, I saw that the link is down.

/ Ports 0-1 of 2   <Main Page>  Copyright(c) <2010-2021>, Intel Corporation
  Flags:Port        : P------Sngl       :0 P------Sngl       :1
Link State          :           <--Down-->           <--Down-->     ---Total Rate---
Pkts/s Rx           :                    0                    0                    0
       Tx           :                    0                    0                    0
MBits/s Rx/Tx       :                  0/0                  0/0                  0/0
Pkts/s Rx Max       :                    0                    0                    0
       Tx Max       :                    0                    0                    0
Broadcast           :                    0                    0
Multicast           :                    0                    0
Sizes 64            :                    0                    0
      65-127        :                    0                    0
      128-255       :                    0                    0
      256-511       :                    0                    0
      512-1023      :                    0                    0
      1024-1518     :                    0                    0
Runts/Jumbos        :                  0/0                  0/0
ARP/ICMP Pkts       :                  0/0                  0/0
Errors Rx/Tx        :                  0/0                  0/0
Total Rx Pkts       :                    0                    0
      Tx Pkts       :                    0                    0
      Rx/Tx MBs     :                  0/0                  0/0
TCP Flags           :               .A....               .A....
TCP Seq/Ack         :  305419896/305419920  305419896/305419920
Pattern Type        :              abcd...              abcd...
Tx Count/% Rate     :           100000 /1%           100000 /1%
Pkt Size/Tx Burst   :            64 /  128            64 /  128
TTL/Port Src/Dest   :       64/ 1234/ 5678       64/ 1234/ 5678
Pkt Type:VLAN ID    :      IPv4 / TCP:0001      IPv4 / TCP:0001
802.1p CoS/DSCP/IPP :            0/  0/  0            0/  0/  0
VxLAN Flg/Grp/vid   :     0000/    0/    0     0000/    0/    0

This is what I have tried with pktgen

sudo cp $pigasus_rep_dir/pigasus/hardware/rtl_sim/input_gen/m10_100.pcap /dev/shm/test.pcap
sudo /opt/pktgen-dpdk/Builddir/app/pktgen -c 0x000000000000003C  -- -P -m "[3].0, [4].1"

I know that the instruction is for Mellanox 100Gbps NIC. On the quartus project, I can see Pigasus using 100G as

I'm newbie with Pigagus and want to try to run with all I have now.
Is it ok to run the test with other NICs like Intel XL710 40Gbps NIC?
Thank you!

Closed Issue

Does ip_gen.tcl connect components?

I have 44 system connectivity errors in the Platform Designer. Attached photo of Platform Designer window.

Also using Platform Designer 19.3 Build 222.

Running Pigasus on a Xilinx FPGA

Hi,

I have a Xilinx Alveo U280 FPGA board. I am trying to synthesize the Pigasus code for the U280 board. Where all will the changes have to be made in order to do so? From what I could figure out, the code in the hardware/rtl_sim/src folder is hardware agnostic. But, in run_ipgen.sh, we specify the exact FPGA board (as Intel Stratix) to be used. How can I port the tcl script (ip_gen.tcl) from Intel Stratix FPGA to a Xilinx U280 FPGA ?

Thanks

error when do the compilation with modelsim

As README sides:

Compile Quartus 19.3 IP library for RTL simulation. Open Quartus 19.3. Select "Launch Simulation Library Compiler" under the "Tools" Tab. Select "ModelSim" as the "Tool name" and specify the path for "Executable location." Then select "Stratix 10" as Library families. Specify the output directory and click "Start Compilation".

after i launched Simulation Library Compiler of Quartus 19.3, and select the tool -> ModelSim, after configuring the element in that page, the error tells me i can not compile simulation lararies if i use ModelSim, beacuse it has precompiled simulation libraries.

so there has a difference with README, so this problem has anyone met? can someone fix my doubts?

thankyou!

Issue with creating ip_gen.qsys

When running shell script run_ipgen.sh, I get an error when the command "qsys-script --script=ip_gen.tcl" is ran.

generate ip cores crash!

why i follow the README.md of pigasus to config my enviroment, but when i did the ./run_ipgen.sh, the process will be stuck at this moment?

and i use the ubuntu 16.04 and quartus 19.3 as the description in REAEDME

crossroadsfpga / pigasus Goto Github PK

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