./run_ipgen.sh failed about pigasus HOT 8 CLOSED

The simulation errors in your last screenshot suggest the simulation library path is not correctly specified. Have you followed the simulation steps in README?

Simulation Setup:

Compile Quartus 19.3 IP library for RTL simulation. Open Quartus 19.3. Select "Launch Simulation Library Compiler" under the "Tools" Tab. Select "ModelSim" as the "Tool name" and specify the path for "Executable location." Then select "Stratix 10" as Library families. Specify the output directory and click "Start Compilation".
Add the compiled library path as the environment variable, by export SIM_LIB_PATH=your_install_path/sim_lib/verilog_libs

Line5-7 of run_vsim.sh requires the path to $SIM_LIB_PATH.

The "errors" in your first three screenshots are expected. We forced qsys to generate those IP core files without connecting those IPs together. This is intended as we only need the individual IP core files. As long as you observe "generated_files" folder is created under $pigasus_repo/pigasus/hardware/scripts/, and there are a list of .sv files as shown below, you should be good.

I'm not sure about the "Killed" you observed after PCIe subsystem is generated. That does not show up on my end. If you just care about simulation, you can actually comment line 17-43 of run_ipgen.sh. Those lines are generating the Ethernet and PCIe subsystems, which are not used in simulation. Also make sure you have installed the Stratix 10 device after installing Quartus 19.3.

One thing I noticed is that the .pcap files in input_gen are missing. Will add them back soon.

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Thanks for your response! I found out that I tried to install the simulation library using Quartus 19.3 by following the instructions, but Quartus showed that "Modelsim-Altera software comes packaged with precompiled simulation libraries", so I do not need to compile (actually it does not allow me to compile). So I tried to find out the sim_lib in the Quartus directory, and I found out the directory "intelFPGA_pro/19.3/quartus/eda/sim_lib". However, this directory seems not to be the one vsim wanted. After running the ./run_vsim.sh again, I got the similar errors reported:

Thanks,
Junzhi

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The Modelsim-Altera and ModelSim are not the same.

We highly recommend running RTL simulation of Pigasus before testing it on real system. Here we use Modelsim-SE (requires license) as our simulation tool. We do not recommend using the Modelsim-Altera_Start_Edition (Modelsim-ASE) -- the free version that comes with Quartus -- to simulate Pigasus, as Pigasus exceeds the line limit of Modelsim-ASE, which leads to extremely slow simulation. We have not tested other simulation tools like VCS.

If you have ModelSim installed, then you will need to do
Select "Launch Simulation Library Compiler" under the "Tools" Tab. Select "ModelSim" as the "Tool name" and specify the path for "Executable location." Then select "Stratix 10" as Library families. Specify the output directory and click "Start Compilation".

If you prefer to use the ModelSim-Altera, then you will need to specify vsim path to point to ModelSim-Altera instead of ModelSim. The compiled sim_lib should be different for these two different tools.

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@zhipengzhaocmu If those errors are expected when generating the IPs we should probably include a note in the README accompanying that command, for others who might come across it.

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@Gavindeed Are you still facing the "Killed" issue, or did you follow @zhipengzhaocmu's recommendation to comment those lines? Could this be because the VM does not have enough memory - PCIe especially is a pretty heavy IP to build, could be a resource issue if it's constrained. Of course also look at the other comments already suggested.

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Thanks for your reply! Zhipeng’s answer is correct that I was not using the correct version of modelsim. I cannot get the modelsim SE so I have to use modelsim ase from Intel. I changed the last line of run_vsim.sh (removing all the $ characters) since modelsim ase has the compiled sim library packaged. I found out it worked. However, it took me two and a half hour to finish the 100 packet simulation instead of 20 seconds shown in the tutorial. Is this time expected? Also I found out it was only using one core to run the simulation, could it be accelerated by using multiple cores?

For the “killed” problem, I temporarily ignored it since the simulation worked for now. But I will try to rerun it by adding more memory resource to the VM. Thanks!

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Thanks for your response!

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