Comments (8)
Hi everyone, thanks for the data points and known issues with 2021.2. Learning about these issues really helps improve the devkit going forward.
We've been prioritizing the 2023.2 AMI release and will update you all as soon as it's ready!
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Hello!
Yes, we're actively working on a customer release to enable Vivado 2023.2.
Does Vivado 2023.2 (or any version since 2021.2) add any new features that you're hoping to use on F1?
Thanks,
-Joe
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I'm also expecting support for the Vitis 2023 release. Specifically, there are bugs fixed for the Task library if we want to implement Task-Channel kernels. I believe the potential benefits are there to updating this repository to keep up with the newer version of Xilinx's development tools.
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@AWSjoeluc : I am also looking forward to support for 2023.2. We are having issues getting our RTL to complete with a simple synth_design -lint
in 2021.2 because of crash with Abnormal program termination (11)
. We face no such issue with 2023.2, and now we are at the stage we want to integrate our CL with the F1 FPGA shell. Having a support for 2023.2 would greatly help us save time in debugging the reason of a crash on a 2 year old version
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It would be great to get 2023.2 supported!
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Really need a newer version of Vitis AMI since there are a lot of bugs in the 2021.2 version. For example, using "pragma dependence off" to specify the false dependency, the synthesis tool would run into infinite loop printing "identified false dependence". This is a crucial feature of our project. Also, some times the use of the vector library would get "conflict pragma of array partition and aggregate", which is a behavior not documented anywhere.
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Related Issues (20)
- DDR performance drop with specific address access pattern HOT 4
- PCIM AXI W Channel hangs with wReady stuck at 0 HOT 2
- Time delay in filling up BRAM using DMA HOT 3
- Clock routing error [Place 30-838] HOT 4
- DMA read is not correct HOT 1
- [XRT] ERROR: failed to load xclbin: Invalid argument / xocl_read_axlf_helper: interface uuids do not match HOT 4
- Inserting ILA is improving the performance HOT 4
- Name port does not exist for instance f1_inst HOT 6
- PCIM ARID all bits can be used? HOT 1
- peer xclbin download err: -11 HOT 2
- fpga_mgmt_load_local_image_sync() failures HOT 12
- Linux Kernel 6 support for xdma HOT 4
- Does aws have u200? HOT 2
- Files missing from AMI HOT 2
- DRAM page mode HOT 1
- Accessing the AXI-Lite via the fpga_pci_attach call... HOT 1
- Debug embedded microblaze using XVC JTAG in AWS FPGA shell HOT 9
- Instance status checks failures HOT 8
- FPGA cloud-based
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