Time delay in filling up BRAM using DMA about aws-fpga HOT 3 CLOSED

Hi,

Filling up the memory is done using DMA as well as the interrupt is also handled by DMA. Both operations concurrently using DMA causing the delay I think so.

Thank you.

from aws-fpga.

Hi @Gogul-N,

I need your help to better understand the issue you have, since it seems very closely related to your receiver design.

It sounds like you have implemented a ping-pong style BRAM access mechanism that once the half of the BRAM data has been fed into the downstream receiver, the half_count will get updated and the other half of the memory will be used to provide data to the downstream receiver while the DMA starts filing up the first half memory again.

And you have two such implementations: one for receiver input data and one for Rx's AGC memory? The issue you're seeing is that the AGC memory gets fed slower? Does that sound like a correct understanding? If not, can you elaborate more to clarify the issue you have?

Thanks,

Chen

from aws-fpga.

Hi @czfpga

Filling up AGC memory is not the problem. When it is not filled, the receiver is not functioning so my half_count is incremented without any issue.

The actual problem is with the interrupt. Interrupt signals from my design was connected to irq_req[15:0]. Here the irq_req[15:0] is handled by DMA Polling. I was trying to listen to the interrupt as well as to fill up the memory inside FPGA using DMA simultaneously using threading function in C. Since both were trying to access the DMA simultaneously the delay was there, I think so.

Thank you.

from aws-fpga.