Clock routing error [Place 30-838] about aws-fpga HOT 4 CLOSED

Hi @ljp0101,

This shouldn't be caused by an out-dated aws-fpga IP. This should be caused by an overly congested design around that reported region. Please refer to this AR for more info (https://support.xilinx.com/s/article/75539?language=en_US)

Have you tried any other strategies listed here: https://github.com/aws/aws-fpga/blob/863d963308231d0789a48f8840ceb1141368b34a/hdk/common/shell_v04261818/new_cl_template/build/README.md, especially the CONGESTION to see it make that help resolve the issue? Thanks.

Chen

from aws-fpga.

@czfpga I'm skeptical it's genuine clock routing congestion at this utilization. Don't have the report available but I did a compile with de minimus logic in the CL beyond the memory controllers and I still got the error so I don't think logic is being forced into particular regions.

+----------------------+--------+-------+--------------+------+-------+------------+-----------+-------+
|       Site Type      | Parent | Child | Non-Assigned | Used | Fixed | Prohibited | Available | Util% |
+----------------------+--------+-------+--------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs |      4 |     9 |            0 |   13 |     0 |          0 |      1200 |  1.08 |
|   BUFGCE             |      4 |     9 |            0 |   13 |     0 |          0 |       480 |  2.71 |
|   BUFGCE_DIV         |      0 |     0 |            0 |    0 |     0 |          0 |        80 |  0.00 |
|   BUFG_GT            |      0 |     0 |            0 |    0 |     0 |          0 |       480 |  0.00 |
|   BUFGCTRL*          |      0 |     0 |            0 |    0 |     0 |          0 |       160 |  0.00 |
| PLL                  |      0 |     9 |            0 |    9 |     0 |          0 |        40 | 22.50 |
| MMCM                 |      1 |     3 |            0 |    4 |     3 |          0 |        20 | 20.00 |
+----------------------+--------+-------+--------------+------+-------+------------+-----------+-------+

Removing phy_opt will solve the problem but I'm going to have to create a custom compile script if I do that because DEFAULT cut the number of processing cores I can pack on the device ~10%.

I'd really like to see if there's an alternative given this seems to be caused by an acknowledged and supposedly resolved Vivado bug. Note the AR says "this issue will be resolved for 2020.2 release of Vivado" and I'm using the latest Developer AMI with 2021.2.

from aws-fpga.

The table above isn't showing any routing resources. That's not what we indicated in previous comment. Please let us know if any strategy or less congested design helped resolve the issue.

from aws-fpga.

Cutting functionality and using one memory controller in the CL was my best option.

The clock routing report isn't saved by the compile script and the checkpoint files were already deleted so I couldn't easily provide it. I shared what I did because I'd be very surprised if there was a clock congestion problem with 13 global clocks and no local clocks in the CL (at least outside the memory controllers), especially given there's not this problem with the DEFAULT flow (but that gives me timing closure issues at the logic utilisation I can get with TIMING).

If you're asking about logic routing, I don't think it should matter but it was the three memory controllers plus another ~1% of slices for my minimal design.

I might want to revisit this later but I'll close as it's moot for now.

from aws-fpga.