zslwyuan / basic-simd-processor-verilog-tutorial Goto Github PK

Sir,
i'm new to verilog and trying to explore and learn. I found SIMD processors interesting and so took it as project.
I have took the source codes made available here and pasted it as it is in Xilin's Vidvado 2020.1 version.
now ideally i though it will working without problems.

But, i have encounter with ERRORS,

in General Section:
[USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Ren.Ps/Documents/VHDL/SIMD/SIMD.sim/sim_1/behav/xsim/elaborate.log' file for more information.

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

In Simulation Section:
[XSIM 43-3230] Could not open sdf file "CPUtop.mapped.sdf".
[XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...

i'm not able to resolve this from weeks now. can you or anyone help me to resolve and get the testebench waveform. plz.

Hi, as you mentioned, each adder block forwards carry bit between other adders. But there is some dependency in here that each adder block waits for the carry to arrive from its previous block. I think would be carry look-aheader adder design to reduce propagation delay instead of current solution.

can you explain how this code is synthesizable?