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icozip's Introduction

ICOZIP

ICO Zip is intended to be a demonstration repository, demonstrating how the ZipCPU may be placed onto an ICO board.

Particular goals of this project include:

  • Generate the main project files using AutoFPGA
  • Demonstrate the ZipCPU running tttt, a 4x4x4 tic-tac-toe game

A unique feature of this project is that the Raspberry Pi that will host the ICO board will only have a minor role in the project. My intention is to use the Raspberry Pi only as a TCP/IP stack the provides access to 1) a command port on the FPGA, 2) a serial port within the FPGA, and perhaps even 3) a means of downloading new bit files to the FPGA. If all goes well, then, one should only need to run the netpport program on the Raspberry Pi, and after that everything should be accessable through the TCP/IP port numbers given in port.h.

This actually has a very profound consequence. By allowing the user to have access to the internals of the FPGA, peripheral development may be done and verified prior to placing the CPU into the FPGA. Hence, by the time the CPU is placed on board, all the parts and pieces of the design will already be known to work, leaving the only new variable that of the CPU itself.

Status

This project is a work in progress, but it is now close enough that if you have an interest in it then I would welcome you to try it.

As of 20170526, the basic, uart, and pmodled examples are fully functional. While much work has taken place on the parallel port testing modules (using sw/netpport)--they just aren't reliable enough (yet) to depend upon.

UPDATE: As of 20180731 ...

  1. The simulator is now fully functional

  2. The CPU test runs. Steps to running the CPU test include:

  • Adjusting sw/host/port.h to contain the network name of your Raspberry Pi. This can be 'localhost' if you intend to do all your work on the Pi.

  • To build the design, you'll need to have verilator, yosys, arachne-pnr, icestorm, wiringPi and the icotools installed. (wiringPi and icotools are ARM-based packages, to be installed on the Pi.) You'll also need the ZipCPU toolchain and AutoFPGA installed and in your path

  • Once the prerequisites have been installed, type 'make' from the main directory.

  • Repeat the build in the sw/host directory from your Raspberry Pi, if this wasn't your build host.

  • Copy the arm-netpport program to the main directory of the Pi.

  • Using icoprog from the icotools package, load the design to the board. icoprog -p < icozip.bin You may need to use sudo depending on how your wiringPi library is set up on your Pi.

  • From the RPi, run arm-netpport. Again, you may need to use sudo for this, depending on your setup.

  • You can then interact with the FPGA using arm-wbregs from another ARM terminal, or pc-wbregs from a PC based host connected over the network. For example, pc-wbregs version will return the date of the build.

  • To run the CPU test, telnet into the RPi at port 8364 to get access to the CPU's console, as in telnet rpi 8364.

  • In another window, type pc-zipload -n rpi -r sw/board/cputest where rpi is the network name/address of your Raspberry Pi. Alternatively, you can type arm-zipload -r sw/board/cputest from a Pi.

  • Look for the results of the CPU test in the console window where you telnet'ed into the CPU on port 8364.

  1. Building the design will also build a simulation in the sim/verilated directory. The main program file for this simulation is automaster_tb.cpp. (The main_tb.cpp file is created by AutoFPGA, and so automaster_tb.cpp is the actual top level program.) You can interact with this simulation just as you would with the CPU. The name of the simulation will either be pc-main_tb or arm-main_tb depending on whether you are running from your host computer or the Pi. pc-main_tb can take an argument -t trace.vcd to force it to create a trace. It can also take the name of a ZipCPU program, which it will then load and automatically run.

  2. I haven't tested flash based programs yet, such as the 4x4x4 tic-tac-toe program mentioned above.

UPDATE: As of 20180801 ...

  1. Flash based programs now run

  2. The ZipCPU debugger has been ported to this architecture

  3. The CPU can now run "Hello, World!" using the newlib C-library, and even starting by copying the program from flash to SRAM

  4. After running cputest, the following are the additional steps necessary to run hello world:

  • The default Makefile should cause a build in sw/zlib, then sw/board

  • This will build hello

  • To run it, load the board and start arm-netpport as you did with the cputest above

  • To capture the output, telnet rpi 8364, or whatever the network address of your Raspberry Pi is.

  • Then run pc-zipload -r sw/board/hello to load and run the program.

  • Watch your telnet session to see the result

  1. You can also run this in a simulation, by running either pc-main_tb path/to/hello, or pc-main_tb and then running pc-zipload -r path/to/hello. You may need to add a -n localhost parameter to your zipload command, and you will need to telnet into your local simulation host, but otherwise running from simulation is the same as from the hardware.

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icozip's Issues

icozip make error

fedora 30 /usr/local/src for default directory
yosys, arachne-pnr, icestorm from repositories

yosys -V
Yosys 0.8 (git sha1 UNKNOWN, gcc 9.0.1 -O2 -fexceptions -fstack-protector-strong -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fPIC -Os)

git clone autofpga and make
autofpga -V
autofpga
built on 20190830

I have copied board.ld and icozip.pcf to auto-fpga directory
then run make which errors after some time

yosys -ql yosys.log -p synth_ice40 -blif icozip.blif -top toplevel ...
toplevel.v:184: ERROR: Identifier \i_clk' is implicitly declared and default_nettype is set to none.

Flash controller

          ![20230921_103408](https://github.com/ZipCPU/icozip/assets/59854753/3f8d6c08-a755-4c7f-aed3-76fae1b89a0a)

Hi dan
How are you?
I'm very happy about your site zipcpu
I had success with the flash controller :) It works with hello sample I used spixscop to debug
My next question is whether after writing the software into the flash why after cpu reset or fpga reset (button) hello sample not running on boot. best regards
Tzahi

Originally posted by @danielitzahi in #5 (comment)

Test sram

Hi dan
in the cputest
Do You test full sram (0-ffff) ?
Best regard
Tzahi

iCE40HX8K-EVB olimex

Hi
Very nice web site Zipcpu
Very nice work
Can i generate project with AutoFpga
For this board iCE40HX8K-EVB olimex
It is very similar to icoboard
Best regard

fedora 31 error with arachne-pnr

I have been testing icozip with fedora 31 , fedora 30 and rpi buster.
This error appears on fedora 31 but not fedora 30.
Not sure if this has anything to do with icozip but asking for advice.

2.46. Executing BLIF backend.

End of script. Logfile hash: f057ca0d26
CPU: user 0.66s system 0.02s, MEM: 50.52 MB total, 44.84 MB resident
Yosys 0.9 (git sha1 UNKNOWN, gcc 9.1.1 -O2 -fexceptions -fstack-protector-strong -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fPIC -Os)
Time spent: 52% 10x read_verilog (0 sec), 14% 1x share (0 sec), ...
arachne-pnr -d 8k -r -P ct256 -p blinky.pcf -o blinky.asc blinky.blif
seed: 2281212662
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
supported packages: bg121, bg121:4k, cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif blinky.blif...
prune...
read_pcf blinky.pcf...
instantiate_io...
pack...

After packing:
IOs 6 / 206
GBs 0 / 8
GB_IOs 0 / 8
LCs 32 / 7680
DFF 3
CARRY 2
CARRY, DFF 24
DFF PASS 0
CARRY PASS 1
BRAMs 0 / 32
WARMBOOTs 0 / 1
PLLs 0 / 2

place_constraints...
promote_globals...
promoted i_clk$2, 27 / 27
promoted 1 nets
1 clk
1 globals
1 clk
realize_constants...
place...
initial wire length = 355
at iteration #50: temp = 12.9827, wire length = 192
at iteration #100: temp = 5.42833, wire length = 132
at iteration #150: temp = 1.43048, wire length = 106
final wire length = 99

After placement:
PIOs 5 / 206
PLBs 8 / 960
BRAMs 0 / 32

place time 0.06s
route...
/usr/include/c++/9/bits/stl_vector.h:1042: std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::operator[](std::vector<_Tp, _Alloc>::size_type) [with _Tp = std::pair<int, int>; _Alloc = std::allocator<std::pair<int, int> >; std::vector<_Tp, _Alloc>::reference = std::pair<int, int>&; std::vector<_Tp, _Alloc>::size_type = long unsigned int]: Assertion '__builtin_expect(__n < this->size(), true)' failed.
make[2]: *** [Makefile:48: blinky.asc] Aborted (core dumped)
rm blinky.blif
make[1]: *** [Makefile:47: basic] Error 2
make: *** [Makefile:158: rtl] Error 2
[pstan@daidokoro-ci-org icozip]$

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