This project will compile verilog (a hardware description language) into factorio blueprints.
Manually compile yosys (since the last release is quite old) and add it to your PATH.
Run npm install
to install all dependencies.
Run npm start ./samples/counter.v
with verilog files as parameters
The compiled blueprint will be output on the command line.
The circuit will have inputs and outputs at the top in the order in which they were written in the code. Clock pulses are required to be exactly one tick high. (since adding edge detectors would produce a lot of overhead)
module counter(input clk, input rst, input inc, output reg [3:0] cnt);
always @(posedge clk) begin
if (rst)
cnt <= 0;
else if (inc)
cnt <= cnt + 1'b1;
end
endmodule
At the top in order clk, rst, inc and cnt.