MIPS-CPU

A Simulative 32-bit CPU Running on MIPS Instruction System Based on Logisim (Newer version Logisim Evolution is not supported). Basic understanding of digital design and MIPS pipelined CPU is strongly recommended ([1] is a great textbook for learning). For more details about implementations please refer to the wiki page.

Two categories of CPU, totaling three implementations, exist in this repository:

Single Cycle CPU: Each instruction takes exactly one CPU cycle to finish. (single_cycle_cpu.circ)
Pipelined CPU: A five-stage pipelined CPU. There are two versions for solving the hazards introduced by pipelining:
1. Pipeline Bubbling for all hazards. (pipeline_cpu_bubbling.circ)
2. Based on Pipeline bubbling, Operand Forwarding is used for data hazards to reduce the total number of pipeline stalls for better performance. (pipeline_cpu.circ).

Note that the common components in src/common are shared among the CPUs, and must be present in the same folder as the CPU circ file for it to work.

The main and most feature-rich version is the pipelined CPU with operand forwarding, which will be referred to as MIPS-CPU in the rest of this README.

Features

Five-Stage Pipeline.
Hazard Handling with Operand Forwarding.
7-Seg Display.
10-bit Address Space for ROM (Code) and RAM (Memory).
Exception Handling: MIPS-CPU (and single cycle CPU) is equipped with a co-processor CP0 which (only) handles exception (interruption), with 3 interruption source buttons named ExpSrc[0-2]. The CPU runs into exception mode on clicking one of the buttons, running an exception service program which displays 2 or 4 or 8 determined by the source number of the clicked button.
Supported Instruction Set:

Instruction	Format	Instruction	Format
Add	add $rd, $rs, $rt	Store Word	sw $rt, offset($rs)
Add Immediate	addi $rt, $rs, immediate	Branch on Equal	beq $rs, $rt, label
Add Immediate Unsigned	addiu $rt, $rs, immediate	Branch on Not Equal	bne $rs, $rt, label
Add Unsigned	addu $rd, $rs, $rt	Set Less Than	slt $rd, $rs, $rt
And	and $rd, $rs, $rt	Set Less Than Immediate	slti $rt, $rs, immediate
And Immediate	andi $rt, $rs, immediate	Set Less Than Unsigned	sltu $rd, $rs, $rt
Shift Left Logical	sll $rd, $rt, shamt	Jump	j label
Shift Right Arithmetic	sra $rd, $rt, shamt	Jump and Link	jal label
Shift Right Logical	srl $rd, $rt, shamt	Jump Register	jr $rs
Sub	sub $rd, $rs, $rt	Syscall (Display or Exit)	syscall
Or	or $rd, $rs, $rt	Move From Co-processor 0	mfc0 $t0,$12
Or Immediate	ori $rt, $rs, immediate	Move To Co-processor 0	mtc0 $t0,$12
Nor	nor $rd, $rs, $rt	Exception Return	eret
Load Word	lw $rt, offset($rs)

Refer to Quick Reference and Complete Instruction Manual from MIPS for complete specifications.

Assembling and Loading Programs

There are many existing MIPS assemblers you can use, we used Mars since it is a powerful MIPS assembler and debugger. Bugs can be easily identified by running Mars to execute the programs instruction by instruction and compare registers, memories, etc. against our CPU implementation. The following steps can be used to obtain an assembled file to be loaded in MIPS-CPU:

Settings -> Memory Configuration, change configuration to Compact, Data Address at 0
Open the assembly code in Mars
Run -> Assemble to assembly the assembly code
File -> Dump Memory and choose Hexadecimal Text as Dump Format
Open the hex file and add a v2.0 raw line at the beginning
The hex file can then be loaded into the ROM part of MIPS-CPU for it to execute

ROMs for Storing Assembled Programs

MIPS-CPU uses 10-bit address space for ROMs. Some special programs, e.g., exception service programs, require a pre-determined fixed address and PC will be set to this address to call service programs when exceptions happen. Therefore, 10-bit address space ROM is implemented via two ROMs with 9-bit address widths, where the most significant bit of the address will be used to switch between the two ROMs. The second ROM (with a start address 0x00000800) then serves the purpose for loading / storing special service programs and cannot be mixed with normal programs. This design makes it really easy to load normal and special service programs in MIPS-CPU.

Example Programs

For normal programs, a benchmark file containing various tests is located at programs/benchmark.asm along with assembled hex file ending with .hex. This benchmark file is preloaded in ROM in all versions of MIPS-CPU. When executed, the 7-seg LED screen will show various patterns and numbers (as showcased in the gif) and at the end show a magic number 0x1CEDCAFE ('iced cafe') to indicate success, if anything went wrong, 0xBAADC0DE ('baad code') will be displayed instead.

For special service programs, an exception service program is provided at programs/exception_service.asm along with assembled hex file. It handles saving environments (including saving PC value to EPC), executing an example service program, and then restore the environments at the end. It supports multi-level interruption by saving everything to a stack in RAM for each level of interruption. This program has to be loaded into the second ROM in MIPS-CPU, which is the special address reserved for the service program. Upon exception, PC will be set to 0x00000800 to run the service program. It is preloaded in the second ROM in all versions of MIPS-CPU that support exception handling.

References

[1] Harris, David, and Sarah Harris. Digital design and computer architecture. Morgan Kaufmann, 2010.

[2] MIPS Quick Reference

[3] MIPS® Architecture for Programmers Volume II-A: The MIPS32® Instruction Set Manual

License

MIT.

ADDIU uses zero extension instead of signed extension on immediate value

I was recently tinkering with mipsel-elf-gcc to compile simple C program and run on a pipelined version of MIPS done by this beautiful implementation in Logisim. I was eager to figure out how MIPS instruction pipelining works in details.

I tried to write program that increments and decrements a value and it turns out that GCC uses addiu instruction for subtraction. So it looks like this from objdump output:

  18:   2402ffff        addiu   v0,zero,-1

It just uses 0xffff in immediate field of ADDIU as -1!

Indeed, the MIPS32 specification on page 36 explicitly mentions that for ADDIU instruction immediate value must be sign-extended (to match destination register bitness, i.e. 32, I guess):

temp <- GPR[rs] + sign_extend(immediate)
GPR[rt] <- temp

That should work as subtraction when the most significant bit of immediate value is 1, even though ADDIU misleadingly has the word "unsigned" in it's name, which may be a little bit misleading.

However in current implementation the part of the opcode decoder that makes zero extension happen instead of sign extension is this:

001001... It is literally just ADDIU! And it indicates IsUnsigned flag that is wrong and misleading, I think.

Actualy there is only 3 instructions in the specification that use zero extension at all - ANDI, ORI, and XORI. All other instructions, that work with immediate values or directly specified offsets, use signed extension.

With that said I suppose the following fix. It addresses all three zero extending instructions:

ANDI 001100
ORI  001101
XORI 001110

Which reduces to expression like this: ZeroExtend = 00110x || 001110

The fixed opcode decoding circuit:

I've made the fix for all three implementations and it at least doesn't brake preloaded test program. You can look at it in the repo I forked, in zero_extend branch (commit permalnk: Oxore@e2bbd2d, browse). If it's OK, I can file a merge request from this branch.

yuxincs / mips-cpu Goto Github PK

mips-cpu's Introduction

MIPS-CPU

Features

Assembling and Loading Programs

ROMs for Storing Assembled Programs

Example Programs

References

License

mips-cpu's People

Contributors

Stargazers

Watchers

Forkers

mips-cpu's Issues

ADDIU uses zero extension instead of signed extension on immediate value

Instruction substitution help

Recommend Projects

React

Vue.js

Typescript

TensorFlow

Django

Laravel

D3

Recommend Topics

javascript

web

server

Machine learning

Visualization

Game

Recommend Org

Facebook

Microsoft

Google

Alibaba

D3

Tencent