check pass falsely warns of undriven wire about yosys HOT 1 CLOSED

When using positional ports (i.e. S S_0 (in[31:24], out[31:24]) instead of S S_0 (.in(in[31:24]), .out(out[31:24])) then you have to run hierarchy before doing anything else with the design. This should always be the first command you execute after reading the design!

Before hierarchy is run on the design you posted, it is not known to yosys which ports on cells like S_0 are inputs or outputs, thus the warnings. (The flatten pass does also resolve positional ports, that's why flatten works without running hierarchy first.)

Btw: Instead of calling something like hierarchy; proc; opt_clean; ... after reading the design you can also simply run prep.

from yosys.