Comments (4)
Printing this error is exactly the expected result for $finish
. The following example demonstrates the how it can be used:
module test(...);
parameter GPIO_COUNT = 16;
...
initial begin
if (GPIO_COUNT < 0 || GPIO_COUNT > 16) begin
$display("Parameter Error: GPIO_COUNT must be in range 0..16");
$finish;
end
end
...
endmodule
from yosys.
In your example, $finish is used as an abort command when parameters etc. are illegal. Then it makes sense to terminate the program during compiling.
In my case, $finish is used for terminating the testbench simulation. As you can see in my provided example, we only simulate 100 time units (#100 $finish;
, the other logic was omitted in the initial block). In this case $finish should only terminate during evaluation, not compilation. Does that mean I should use something else like $stop instead of $finish here?
from yosys.
I don't really understand why you are trying to synthesize your testbench. In synthesis, all #
-delays are ignored, so your example effectively contains initial $finish;
.
from yosys.
Hmm, I see your point. I imported the whole source tree by read_verilog
, which happened to include the testbench files. Afterwards I call hierarchy
to specify the top design.
I just took another look at the document, and used -defer
option in read_verilog
to avoid this problem. Thanks!
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