Comments (3)
Since I'm not a synopsys user myself I can't say if there is a complete publicly available library of those cells. But there are some liberty files that implement at least what seems to be a subset. For example: http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
For example with that liberty file, and a structural netlist synth.v, you can do the following to replace the library cells in the design with their definitions from the cell library:
# read structural netlist
read_verilog synth.v
# replace library cells
read_liberty -setattr libcells osu025_stdcells.lib
flatten A:libcells %C
delete A:libcells
(This requires git head. I've just implemented the select operator %C in commit 8eadd8f because I realized that this functionality was missing when I started to answer your question.)
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Could you explain how this is different than using techmap?
from yosys.
Techmap and flatten actually share the same codebase. So its not different at all. But techmap can only read verilog and ilang files at the moment, so it was not the first thing I thought of and then I decided I wanted to implement the %C (and %M) select operators..
You are right: using techmap would actually be much better. (And works with yosys-0.5 just fine.)
So you would either convert the liberty file to ilang first:
read_liberty osu025_stdcells.lib
write_ilang libcells.il
design -reset
read_verilog synth.v
techmap -map libcells.il
Or (a bit cleaner imo) use separate designs in memory:
read_liberty osu025_stdcells.lib
design -stash libcells
read_verilog synth.v
techmap -map %libcells
So that's proof that just because I wrote the software doesn't mean that I always intuitively know how to use it best.. :)
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Related Issues (20)
- Crash in yosys-abc HOT 1
- Manual title page should have yosys version number
- Should -nomx8 be the default for the GateMate?
- opt: no "-purge" option but public names removed HOT 2
- Tests fails on Debian GNU/Linux on ppc64 HOT 6
- write_smt2: "-wires" option leads to inequivalent descriptions
- Spurious warnings "select out of bounds on signal" when there is no such thing ... HOT 1
- Inconsistent simulation before and after yosys synthesis HOT 1
- Inout can't be read with constant value HOT 3
- Inout port not working with array replication operator HOT 6
- Add support for SystemVerilog's `==?` and `!=?` operators
- Unexpected Result from `synth_gowin` Pass HOT 4
- No bad property in btor2 file generated from verilog (`write_btor` should error for `$check` cells) HOT 3
- Build error: `make: *** [Makefile:810: abc/abc] Error 2` HOT 4
- Documentation is unreadable if the system theme is dark HOT 5
- Wired-or (wor) wires generate $or / $reduce_or cells in output HOT 3
- Nothing of abc folder contents at git clone https://github.com/YosysHQ/yosys.git HOT 1
- Yosys seems to handle bit operations on empty strings inconsistently with the original design. HOT 4
- The negation operation on an empty string results in an exception. HOT 6
- Outputs differ before and after synthesis, but Yosys seems correct.
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from yosys.