Comments (12)
Siesh1oo
commented on August 18, 2024
One more note: double-checking the unmodified git from https://github.com/cliffordwolf/ on the Linux box exposes the same error, creating a diff will show only a difference in the GIT tag; otherwise the files are identical:
diff ~/yosys/tests/techmap/mem_simple_4x1_synth.v mem_simple_4x1_synth.v
1c1
< /* Generated by Yosys 0.2.0+ (git sha1 876c016) */
---
> /* Generated by Yosys 0.2.0+ (git sha1 78c64a6) */
Testing with an older iverilog git version (0.10.0) on OSX gives even different line numbers (57, 59, 62, 64, 65, 66, 67, 214, 215, 216). To give an impression about the difference in the output files, here the first few lines on the Linux box (disregarding the GIT sha1, identical for unmodified git and the tree including the OSX-related changes):
/* Generated by Yosys 0.2.0+ (git sha1 876c016) */
(* src = "mem_simple_4x1_uut.v:1" *)
module uut(clk, rst, out, counter);
(* src = "mem_simple_4x1_uut.v:9" *)
wire [4:0] _00_;
wire _01_;
wire _02_;
wire _03_;
reg _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
On OSX:
/* Generated by Yosys 0.2.0+ (git sha1 876c016) */
(* src = "mem_simple_4x1_uut.v:1" *)
module uut(clk, rst, out, counter);
(* src = "mem_simple_4x1_uut.v:9" *)
wire [4:0] _00_;
(* src = "mem_simple_4x1_uut.v:10" *)
wire [31:0] _01_;
(* src = "mem_simple_4x1_uut.v:10" *)
wire _02_;
(* src = "mem_simple_4x1_uut.v:10" *)
wire _03_;
(* src = "mem_simple_4x1_map.v:113" *)
reg _04_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _05_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _06_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _07_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _08_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _09_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _10_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _11_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _12_;
(* src = "mem_simple_4x1_map.v:86" *)
wire _13_;
(* src = "mem_simple_4x1_map.v:86" *)
So in summary, this test case seems to expose two issues:
- problems with iverilog parsing the attribute (which versions are known to work?)
- nondeterministic synthesis, the attributes on Linux are not generated as consistently as on OSX/BSD.
It might seem noteworthy that the iverilog parse error is not happening at the first attribute occurrence in the file.
from yosys.
Siesh1oo
commented on August 18, 2024
The latest iverilog snapshot (GIT 0.10.0 (devel) (s20121218-439-gbc9382e)) passes the test (but comes with broken configure script and does not build out of the box).
Might it make sense to build iverilog within the tree like abc, so that known working versions are bundled?
The open question remains why the synthesis results on Linux contain fewer attributes...
from yosys.
cliffordwolf
commented on August 18, 2024
Yes, older iverilog versions don't like attributes (different versions of iverilog support attributes in more or fewer places). All the other test cases call the verilog backend with -noattr, but for the mem_simple_4x1 test I forgot it. I've now pushed a fix for that.
Regarding the difference in number of attributes between Linux and OSX: This should of course not be this way. Unfortunately I don't have access to an OSX machine, so I can't hunt this bug down. So I am asking you to run a few tests. Could you please compare the output of the following commands between Linux and OSX:
cd tests/techmap
../../yosys -b ilang -p 'proc' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt; memory -nomap' mem_simple_4x1_uut.v
[ ... ]
../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
from yosys.
Siesh1oo
commented on August 18, 2024
Will do later today when I have access to the box again. My first guess was "uninitialized variable/memory?" -- is yosys tested using valgrind or a similar tool on a regular basis?
from yosys.
cliffordwolf
commented on August 18, 2024
I use valgrind on occasion. I ran it on that command now and found and fixed one unrelated bug.. ;)
from yosys.
Siesh1oo
commented on August 18, 2024
Maybe it's sensible to make it part of the nightly regression or make it an autotest.sh option?
Concerning the different iverilog versions (and similar potential problems on other simulators): would it make sense to have an option to select the src-reference format (none, /src=comment/, (src=attr), src=preprocessor-`line so that the synthesis output of high-level tools will automatically reference the high-level source file)? All three flavors might have their merits in some circumstances...
from yosys.
cliffordwolf
commented on August 18, 2024
The Verilog backend provides the option -attr2comment that causes the attributes to be dumped as verilog comments. The backend has no idea what the attribute "src" means.
Btw: I've now added support for `line directive to the Verilog frontend.
from yosys.
Siesh1oo
commented on August 18, 2024
That's great, have seen the patch just a second ago!
from yosys.
Siesh1oo
commented on August 18, 2024
For this test:
cd tests/techmap
../../yosys -b ilang -p 'proc' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt; memory -nomap' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc' mem_simple_4x1_uut.v
../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
we get this diff between OSX and Linux log (absolute Linux path names are shortened):
--- yosys-OSX.log 2014-03-11 23:28:23.000000000 +0100
+++ yosys-Linux.log 2014-03-11 23:30:33.000000000 +0100
@@ -73,8 +73,6 @@ Cleaned up 0 empty switches.
3. Executing ILANG backend.
Output filename: <stdout>
-
-READY.
# Generated by Yosys 0.2.0+ (git sha1 59239f6)
attribute \src "mem_simple_4x1_uut.v:1"
module \uut
@@ -191,7 +189,9 @@ module \uut
attribute \src "mem_simple_4x1_uut.v:9"
cell $dff $procdff$14
parameter \CLK_POLARITY 1'1
- parameter \WIDTH 1
+ parameter \WI
+READY.
+DTH 1
connect \CLK \clk
connect \D 1'1
connect \Q $memwr$\memory$mem_simple_4x1_uut.v:11$1_EN
@@ -226,7 +226,7 @@ module \uut
connect $0$memwr$\memory$mem_simple_4x1_uut.v:11$1_EN[0:0]$5 1'1
connect $0\out[7:0] $memrd$\memory$mem_simple_4x1_uut.v:12$10_DATA
end
-+ ../../yosys -b ilang -p 'proc; opt' mem_simple_4x1_uut.v
++ ../../yosys -b ilang -p proc; opt mem_simple_4x1_uut.v
/-----------------------------------------------------------------------------\
| |
@@ -363,8 +363,6 @@ Finding unused cells or wires in module
4. Executing ILANG backend.
Output filename: <stdout>
-
-READY.
# Generated by Yosys 0.2.0+ (git sha1 59239f6)
attribute \src "mem_simple_4x1_uut.v:1"
module \uut
@@ -490,11 +488,13 @@ module \uut
parameter \WIDTH 32
connect \A $add$mem_simple_4x1_uut.v:10$8_Y
connect \B 0
- connect \S $logic_or$mem_simple_4x1_uut.v:10$7_Y
+ connect \S $log
+READY.
+ic_or$mem_simple_4x1_uut.v:10$7_Y
connect \Y { $ternary$mem_simple_4x1_uut.v:10$9_Y [31:5] $0\counter[4:0] }
end
end
-+ ../../yosys -b ilang -p 'proc; opt; memory -nomap' mem_simple_4x1_uut.v
++ ../../yosys -b ilang -p proc; opt; memory -nomap mem_simple_4x1_uut.v
/-----------------------------------------------------------------------------\
| |
@@ -766,7 +766,7 @@ module \uut
connect \Y { $ternary$mem_simple_4x1_uut.v:10$9_Y [31:5] $0\counter[4:0] }
end
end
-+ ../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v' mem_simple_4x1_uut.v
++ ../../yosys -b ilang -p proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v mem_simple_4x1_uut.v
/-----------------------------------------------------------------------------\
| |
@@ -2129,20 +2129,20 @@ module \uut
connect $techmap30$mem$\memory$18.slice[1].bit_slice.part_low._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap31$mem$\memory$18.slice[2].bit_slice.part_high._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap32$mem$\memory$18.slice[2].bit_slice.part_low._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
- connect $techmap33$mem$\memory$18.slice[3].bit_sl
-READY.
-ice.part_high._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
+ connect $techmap33$mem$\memory$18.slice[3].bit_slice.part_high._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap34$mem$\memory$18.slice[3].bit_slice.part_low._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap35$mem$\memory$18.slice[4].bit_slice.part_high._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap36$mem$\memory$18.slice[4].bit_slice.part_low._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap37$mem$\memory$18.slice[5].bit_slice.part_high._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap38$mem$\memory$18.slice[5].bit_slice.part_low._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap39$mem$\memory$18.slice[6].bit_slice.part_high._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
- connect $techmap40$mem$\memory$18.slice[6].bit_slice.part_low._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
+ connect $techmap40$mem$\memory$18.slice[6].bit_slice.part_low._TECHMAP_DONE_ 1024'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+READY.
+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap41$mem$\memory$18.slice[7].bit_slice.part_high._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
connect $techmap42$mem$\memory$18.slice[7].bit_slice.part_low._TECHMAP_DONE_ 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000001110010011011110110001100111011001000000110001101101100011001010110000101101110
end
-+ ../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap' mem_simple_4x1_uut.v
++ ../../yosys -b ilang -p proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap mem_simple_4x1_uut.v
/-----------------------------------------------------------------------------\
| |
@@ -3981,9 +3981,7 @@ module \uut
connect \Y $add$mem_simple_4x1_uut.v:10$8_Y [2]
end
attribute \src "<stdcells.v>:417"
- cell $_OR_ $add$mem_
-READY.
-simple_4x1_uut.v:10$8.alu.V[2].adder.gate5
+ cell $_OR_ $add$mem_simple_4x1_uut.v:10$8.alu.V[2].adder.gate5
connect \A $add$mem_simple_4x1_uut.v:10$8.alu.V[2].adder.t1
connect \B $add$mem_simple_4x1_uut.v:10$8.alu.V[2].adder.t3
connect \Y $add$mem_simple_4x1_uut.v:10$8.alu.carry [3]
@@ -4802,7 +4800,9 @@ simple_4x1_uut.v:10$8.alu.V[2].adder.gat
connect \WR_EN $techmap$mem$\memory$18.slice[3].bit_slice.$logic_and$mem_simple_4x1_map.v:111$23_Y
end
attribute \src "mem_simple_4x1_map.v:118"
- cell \MEM4X1 $mem$\memory$18.slice[4].bit_slice.part_high
+ cell \MEM4X1 $mem$\memory$18.slice[
+READY.
+4].bit_slice.part_high
connect \CLK \clk
connect \RD_ADDR \counter [3:0]
connect \RD_DATA $mem$\memory$18.slice[4].bit_slice.high_rd_data
@@ -4882,7 +4882,7 @@ simple_4x1_uut.v:10$8.alu.V[2].adder.gat
connect $eq$mem_simple_4x1_uut.v:10$6.A_buf \counter
connect $eq$mem_simple_4x1_uut.v:10$6.B_buf 5'10011
end
-+ ../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt' mem_simple_4x1_uut.v
++ ../../yosys -b ilang -p proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt mem_simple_4x1_uut.v
/-----------------------------------------------------------------------------\
| |
@@ -5661,8 +5661,6 @@ Finding unused cells or wires in module
8. Executing ILANG backend.
Output filename: <stdout>
-
-READY.
# Generated by Yosys 0.2.0+ (git sha1 59239f6)
attribute \src "mem_simple_4x1_uut.v:1"
module \uut
@@ -6054,7 +6052,9 @@ module \uut
connect \RD_ADDR \counter [3:0]
connect \RD_DATA $mem$\memory$18.slice[6].bit_slice.low_rd_data
connect \WR_ADDR \counter [3:0]
- connect \WR_DATA 1'0
+ conne
+READY.
+ct \WR_DATA 1'0
connect \WR_EN $techmap$mem$\memory$18.slice[0].bit_slice.$logic_and$mem_simple_4x1_map.v:111$23_Y
end
attribute \src "mem_simple_4x1_map.v:118"
@@ -6076,7 +6076,7 @@ module \uut
connect \WR_EN $techmap$mem$\memory$18.slice[0].bit_slice.$logic_and$mem_simple_4x1_map.v:111$23_Y
end
end
-+ ../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc' mem_simple_4x1_uut.v
++ ../../yosys -b ilang -p proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc mem_simple_4x1_uut.v
/-----------------------------------------------------------------------------\
| |
@@ -6853,14 +6853,14 @@ Finding unused cells or wires in module
8. Executing ABC pass (technology mapping using ABC).
-8.1. Extracting gate netlist of module `\uut' to `/tmp/yosys-abc-zdBac9/input.blif'..
+8.1. Extracting gate netlist of module `\uut' to `/tmp/yosys-abc-HCJaEJ/input.blif'..
Extracted 30 gates and 55 wires to a netlist network with 23 inputs and 14 outputs.
8.1.1. Executing ABC.
-yosys-abc -s -c 'read_blif /tmp/yosys-abc-zdBac9/input.blif; read_library /tmp/yosys-abc-zdBac9/stdcells.genlib; source /tmp/yosys-abc-zdBac9/abc.script; write_blif /tmp/yosys-abc-zdBac9/output.blif' 2>&1
-ABC: ABC command line: "read_blif /tmp/yosys-abc-zdBac9/input.blif; read_library /tmp/yosys-abc-zdBac9/stdcells.genlib; source /tmp/yosys-abc-zdBac9/abc.script; write_blif /tmp/yosys-abc-zdBac9/output.blif".
+yosys/yosys-abc -s -c 'read_blif /tmp/yosys-abc-HCJaEJ/input.blif; read_library /tmp/yosys-abc-HCJaEJ/stdcells.genlib; source /tmp/yosys-abc-HCJaEJ/abc.script; write_blif /tmp/yosys-abc-HCJaEJ/output.blif' 2>&1
+ABC: ABC command line: "read_blif /tmp/yosys-abc-HCJaEJ/input.blif; read_library /tmp/yosys-abc-HCJaEJ/stdcells.genlib; source /tmp/yosys-abc-HCJaEJ/abc.script; write_blif /tmp/yosys-abc-HCJaEJ/output.blif".
ABC:
-ABC: Entered genlib library with 8 gates from file "/tmp/yosys-abc-zdBac9/stdcells.genlib".
+ABC: Entered genlib library with 8 gates from file "/tmp/yosys-abc-HCJaEJ/stdcells.genlib".
ABC: + strash
ABC:
ABC: + scorr -v
@@ -6900,20 +6900,20 @@ ABC: SAT solver: Vars = 63. Max cone = 0
ABC: SAT calls : All = 16. Unsat = 16. Sat = 0. Fail = 0.
ABC: Choices : Lits = 26. Reprs = 0. Equivs = 0. Choices = 0.
ABC: Choicing runtime statistics:
-ABC: Sim init = 0.00 sec ( 5.12 %)
+ABC: Sim init = 0.00 sec ( 8.19 %)
ABC: Sim SAT = 0.00 sec ( 0.00 %)
-ABC: SAT solving = 0.00 sec ( 14.74 %)
+ABC: SAT solving = 0.00 sec ( 20.16 %)
ABC: sat = 0.00 sec ( 0.00 %)
-ABC: unsat = 0.00 sec ( 15.85 %)
+ABC: unsat = 0.00 sec ( 20.55 %)
ABC: undecided = 0.00 sec ( 0.00 %)
ABC: Choice = 0.00 sec ( 0.00 %)
-ABC: Other = 0.00 sec ( 80.14 %)
+ABC: Other = 0.00 sec ( 71.65 %)
ABC: TOTAL = 0.00 sec (100.00 %)
ABC: Synthesis = 0.00 sec
ABC: STATS: Ands: 99 -> 89. Reprs: 26 -> 16. Choices = 15.
ABC:
ABC: + map -v
-ABC: Converting "/tmp/yosys-abc-zdBac9/stdcells.genlib" into supergate library "/tmp/yosys-abc-zdBac9/stdcells.super".
+ABC: Converting "/tmp/yosys-abc-HCJaEJ/stdcells.genlib" into supergate library "/tmp/yosys-abc-HCJaEJ/stdcells.super".
ABC: Performing mapping with choices.
ABC: Maximum level: Original = 6. Reduced due to choices = 6.
ABC: Choice stats: Choice nodes = 15. Total choices = 31.
@@ -6927,7 +6927,7 @@ ABC: Output n51 : Delay = ( 5.00, 5
ABC: Output n52 : Delay = ( 5.00, 5.00) POS
ABC: Output n53 : Delay = ( 5.00, 5.00) POS
ABC: Output n54 : Delay = ( 5.00, 5.00) POS
-ABC: Total runtime = 0.01 sec
+ABC: Total runtime = 0.00 sec
8.1.2. Re-integrating ABC results.
ABC RESULTS: AND cells: 9
@@ -6939,19 +6939,17 @@ ABC RESULTS: internal signals:
ABC RESULTS: input signals: 23
ABC RESULTS: output signals: 14
-8.1.3. Removing temp directory `/tmp/yosys-abc-zdBac9':
-Removing `/tmp/yosys-abc-zdBac9/abc.script'.
-Removing `/tmp/yosys-abc-zdBac9/input.blif'.
-Removing `/tmp/yosys-abc-zdBac9/output.blif'.
-Removing `/tmp/yosys-abc-zdBac9/stdcells.genlib'.
-Removing `/tmp/yosys-abc-zdBac9'.
+8.1.3. Removing temp directory `/tmp/yosys-abc-HCJaEJ':
+Removing `/tmp/yosys-abc-HCJaEJ/abc.script'.
+Removing `/tmp/yosys-abc-HCJaEJ/input.blif'.
+Removing `/tmp/yosys-abc-HCJaEJ/output.blif'.
+Removing `/tmp/yosys-abc-HCJaEJ/stdcells.genlib'.
+Removing `/tmp/yosys-abc-HCJaEJ'.
-- Writing to stdout using backend `ilang' --
9. Executing ILANG backend.
Output filename: <stdout>
-
-READY.
# Generated by Yosys 0.2.0+ (git sha1 59239f6)
attribute \src "mem_simple_4x1_uut.v:1"
module \uut
@@ -7409,7 +7407,9 @@ module \uut
connect \out [0] $abc$208$n27
connect $abc$208$n28 $mem$\memory$18.slice[1].bit_slice.low_rd_data
connect $abc$208$n29 $mem$\memory$18.slice[1].bit_slice.high_rd_data
- connect \out [1] $abc$208$n30
+ co
+READY.
+nnect \out [1] $abc$208$n30
connect $abc$208$n31 $mem$\memory$18.slice[2].bit_slice.low_rd_data
connect $abc$208$n32 $mem$\memory$18.slice[2].bit_slice.high_rd_data
connect \out [2] $abc$208$n33
@@ -7434,7 +7434,7 @@ module \uut
connect $0\counter[4:0] [3] $abc$208$n53
connect $0\counter[4:0] [4] $abc$208$n54
end
-+ ../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
++ ../../yosys -b ilang -p proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat mem_simple_4x1_uut.v
/-----------------------------------------------------------------------------\
| |
@@ -8211,14 +8211,14 @@ Finding unused cells or wires in module
8. Executing ABC pass (technology mapping using ABC).
-8.1. Extracting gate netlist of module `\uut' to `/tmp/yosys-abc-PEHipu/input.blif'..
+8.1. Extracting gate netlist of module `\uut' to `/tmp/yosys-abc-jzPH7F/input.blif'..
Extracted 30 gates and 55 wires to a netlist network with 23 inputs and 14 outputs.
8.1.1. Executing ABC.
-yosys-abc -s -c 'read_blif /tmp/yosys-abc-PEHipu/input.blif; read_library /tmp/yosys-abc-PEHipu/stdcells.genlib; source /tmp/yosys-abc-PEHipu/abc.script; write_blif /tmp/yosys-abc-PEHipu/output.blif' 2>&1
-ABC: ABC command line: "read_blif /tmp/yosys-abc-PEHipu/input.blif; read_library /tmp/yosys-abc-PEHipu/stdcells.genlib; source /tmp/yosys-abc-PEHipu/abc.script; write_blif /tmp/yosys-abc-PEHipu/output.blif".
+yosys/yosys-abc -s -c 'read_blif /tmp/yosys-abc-jzPH7F/input.blif; read_library /tmp/yosys-abc-jzPH7F/stdcells.genlib; source /tmp/yosys-abc-jzPH7F/abc.script; write_blif /tmp/yosys-abc-jzPH7F/output.blif' 2>&1
+ABC: ABC command line: "read_blif /tmp/yosys-abc-jzPH7F/input.blif; read_library /tmp/yosys-abc-jzPH7F/stdcells.genlib; source /tmp/yosys-abc-jzPH7F/abc.script; write_blif /tmp/yosys-abc-jzPH7F/output.blif".
ABC:
-ABC: Entered genlib library with 8 gates from file "/tmp/yosys-abc-PEHipu/stdcells.genlib".
+ABC: Entered genlib library with 8 gates from file "/tmp/yosys-abc-jzPH7F/stdcells.genlib".
ABC: + strash
ABC:
ABC: + scorr -v
@@ -8258,20 +8258,20 @@ ABC: SAT solver: Vars = 63. Max cone = 0
ABC: SAT calls : All = 16. Unsat = 16. Sat = 0. Fail = 0.
ABC: Choices : Lits = 26. Reprs = 0. Equivs = 0. Choices = 0.
ABC: Choicing runtime statistics:
-ABC: Sim init = 0.00 sec ( 4.36 %)
+ABC: Sim init = 0.00 sec ( 6.73 %)
ABC: Sim SAT = 0.00 sec ( 0.00 %)
-ABC: SAT solving = 0.00 sec ( 16.25 %)
+ABC: SAT solving = 0.00 sec ( 20.05 %)
ABC: sat = 0.00 sec ( 0.00 %)
-ABC: unsat = 0.00 sec ( 17.40 %)
+ABC: unsat = 0.00 sec ( 20.60 %)
ABC: undecided = 0.00 sec ( 0.00 %)
ABC: Choice = 0.00 sec ( 0.00 %)
-ABC: Other = 0.00 sec ( 79.39 %)
+ABC: Other = 0.00 sec ( 73.21 %)
ABC: TOTAL = 0.00 sec (100.00 %)
-ABC: Synthesis = 0.01 sec
+ABC: Synthesis = 0.00 sec
ABC: STATS: Ands: 99 -> 89. Reprs: 26 -> 16. Choices = 15.
ABC:
ABC: + map -v
-ABC: Converting "/tmp/yosys-abc-PEHipu/stdcells.genlib" into supergate library "/tmp/yosys-abc-PEHipu/stdcells.super".
+ABC: Converting "/tmp/yosys-abc-jzPH7F/stdcells.genlib" into supergate library "/tmp/yosys-abc-jzPH7F/stdcells.super".
ABC: Performing mapping with choices.
ABC: Maximum level: Original = 6. Reduced due to choices = 6.
ABC: Choice stats: Choice nodes = 15. Total choices = 31.
@@ -8297,12 +8297,12 @@ ABC RESULTS: internal signals:
ABC RESULTS: input signals: 23
ABC RESULTS: output signals: 14
-8.1.3. Removing temp directory `/tmp/yosys-abc-PEHipu':
-Removing `/tmp/yosys-abc-PEHipu/abc.script'.
-Removing `/tmp/yosys-abc-PEHipu/input.blif'.
-Removing `/tmp/yosys-abc-PEHipu/output.blif'.
-Removing `/tmp/yosys-abc-PEHipu/stdcells.genlib'.
-Removing `/tmp/yosys-abc-PEHipu'.
+8.1.3. Removing temp directory `/tmp/yosys-abc-jzPH7F':
+Removing `/tmp/yosys-abc-jzPH7F/abc.script'.
+Removing `/tmp/yosys-abc-jzPH7F/input.blif'.
+Removing `/tmp/yosys-abc-jzPH7F/output.blif'.
+Removing `/tmp/yosys-abc-jzPH7F/stdcells.genlib'.
+Removing `/tmp/yosys-abc-jzPH7F'.
Removed 0 unused cells and 48 unused wires.
9. Printing statistics.
@@ -8330,8 +8330,6 @@ Removed 0 unused cells and 48 unused wir
10. Executing ILANG backend.
Output filename: <stdout>
-
-READY.
# Generated by Yosys 0.2.0+ (git sha1 59239f6)
attribute \src "mem_simple_4x1_uut.v:1"
module \uut
@@ -8603,7 +8601,9 @@ module \uut
connect \WR_EN \counter [4]
end
attribute \src "mem_simple_4x1_map.v:118"
- cell \MEM4X1 $mem$\memory$18.slice[2].bit_slice.part_low
+ cell \MEM4X1 $mem$\memory$18.slice[2
+READY.
+].bit_slice.part_low
connect \CLK \clk
connect \RD_ADDR \counter [3:0]
connect \RD_DATA $abc$208$n31
from yosys.
cliffordwolf
commented on August 18, 2024
The only differences I see here are (1) because the shells use different formats in their set -x output and (2) because the stdout vs. stderr buffering is different on both platforms, so the "READY." is moved to different locations.
So just to be clear: the output of
../../yosys -b ilang -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
is identical on both platforms but the output of
../../yosys -b verilog -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
is different? Could you please double-check that? If so, the code that behaves differently is somewhere in the verilog backend. But at a quick glimpse I can't find anything there that could cause this..
from yosys.
Siesh1oo
commented on August 18, 2024
Now they are equal (both like the reported Linux output above, the first attribute before line 41). Remembering my steps yesterday, it comes to my mind that I found and fixed the 'od' problem in passes/techmap/Makefile.inc, that generates the stdcells.inc file, after reporting this bug.
So the std cells include template was broken and the output was likely to be invalid at this point, even if the test suite reported no failure? Could this be possible? Is the test suite referencing any absolute golden input that is not generated using the possibly broken toolchain under test?
What would happen if the array/string in passes/.../stdcells.inc is empty and contains only the terminating null-byte?
from yosys.
cliffordwolf
commented on August 18, 2024
What would happen if the array/string in passes/.../stdcells.inc is empty and contains only the terminating null-byte?
Then the techmap command would be a no-op. The test cases would still return OK because the post-synthesis simulation matches the pre-synthesis simulation. But yosys-bigsim would fail because the scripts there check if the synthesis result only contains primitive logic gates.
from yosys.
Related Issues (20)
- Feature Request: Add Support for Input Filelist Option HOT 8
- CologneChip synthesis fails silently (simulation discrepancies) HOT 2
- Yosys Synthesis Error: Hash Table Exceeded Maximum Size HOT 8
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- Unable to code FSM into binary format HOT 2
- Can't build from 0.42 tarball HOT 1
- ABC: execution of command failed return code 139. HOT 3
- Variable Part Selects HOT 5
- ABC: execution of command failed return code 137. HOT 5
- Yosys Optimization Error: Optimization Stuck in PEEPOPT Pass HOT 2
- Yosys Optimization Issue: Process Stuck at OPT_CLEAN Pass HOT 1
- Build issue with abc submodule HOT 2
- Optimization Sequence Induces Synthesis Errors Leading to Simulation Inconsistencies HOT 10
- Optimization Sequence Leads to Functionally Incorrect Synthesis Output in Yosys HOT 1
- Custom Yosys Passes Result in Faulty Synthesis and Simulation Errors HOT 5
- Any plans to add CDC linting? HOT 9
- yosys -sim hangs on multiple writes to the same memory address
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