Comments (3)
It seems that the $mem
refers to an instance of the following verilog module (pulled out of the source for convenience). I did some reading and it seems that yosys supports compiling behavioral verilog to the ice40 BRAMs, but perhaps there's something about this module that is causing the issue.
module coreir_mem #(parameter depth=1, parameter has_init=1, parameter width=1) (
input clk,
input [width-1:0] wdata,
input [$clog2(depth)-1:0] waddr,
input wen,
output reg [width-1:0] rdata,
input [$clog2(depth)-1:0] raddr
);
reg [width-1:0] data[depth-1:0];
always @(posedge clk) begin
if (wen) begin
data[waddr] <= wdata;
end
end
assign rdata = data[raddr];
endmodule //coreir_mem
Here is the instantiation from line 1442 of the source verilog
coreir_mem #(.depth(16),.has_init(0),.width(8)) mem(
.clk(mem__clk),
.raddr(mem__raddr),
.rdata(mem__rdata),
.waddr(mem__waddr),
.wdata(mem__wdata),
.wen(mem__wen)
);
from arachne-pnr.
The line
assign rdata = data[raddr];
defines a RAM with an asynchronous read port, which is not supported in the iCE40 hardware. Hence Yosys is unable to map it to the iCE40 primitive (tbh I would have expected it to smash it into DFFs and LUTs).
from arachne-pnr.
Got it, makes sense. So we will work around this by changing our memory to have a synchronous read, thanks!
from arachne-pnr.
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from arachne-pnr.