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Reverse engineering Neo Geo 161 in 1 cartridge to change Rom games

C 99.45% Assembly 0.17% Batchfile 0.01% Pascal 0.15% Verilog 0.09% Tcl 0.01% Python 0.14%

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twistedtom raschinger helder1981 tawyy dangermousehouse jwestfall69 mcbeengs rolel yakaracolombia leonkiriliuk mancloud

vtxcart's Issues

Feature: add clones without cloning C/V ROM

Hello,

As original 161in1 setup, it would be nice to be able to add some clones without using C/V rom space. I think about MetalSlub2 / 2Turbo, Shocktroopers that exists with 2 P1rom that don't score the same way, and maybe not "creepy" ROM hack.

I didn't had a look deep into compiler, currently I only suggest the idea. Any guideline and advice is appreciated.

Regards

Programmer

Hi, which of these 4 boards do I need to flash the 161in1 cardridge. Would it be also possible to add an "how to". Thanks as always for your great work.
Cheers

CPLD: Detect Reset and remap menu

Dear Vortex,

I'd like to implement a "back-to-menu" function upon soft- or hard-reset into the CPLD.
Do you have any information about how to detect a reset from the cartslot?

Thank you very much!

CV_DIP Dumper spacing issue

I have a MVS 161in1 that has the 1.27mm dip style daughter boards for the C and V flash chips. There seems to be a spacing issue with the distance between the 2 double rows of 1.27mm holes on the CV_DIP dumper board.

The below pictures are comparing the double row spacing between the 161in1 board and the CV_DIP dumper board. I'm using 2 pieces of wire to align the left side double rows between the boards. However you can see the right side double row of the CV_DIP dumper are offset to the right by about 1/2 a hole compared to the 161in1's holes.

zoomed in more

This extra distance between the left/right double rows of the CV_DIP is enough to make it impossible to insert the daughter board.

checkgames.bat

Here's a handy bat that checks the games.txt against the contents of the Games folder.
Save to Compiler\bin.

Checks every folder contained in games.txt if a prom file exists
Ignores entries starting with #

@echo off
setlocal enabledelayedexpansion
cls
set "allExist=true"

for /F "delims=" %%a in (games.txt) do (
    set "folderName=%%a"
    if "!folderName:~0,1!" NEQ "#" (
        if not exist "..\Games\%%a\prom" (
            echo Missing files or folder: %%a
            set "allExist=false"
        )
    )
)

if "%allExist%"=="true" (
    echo All folders contained in games.txt exist in the Games folder!
)

endlocal

REM run this bat from VTXCart-main / Compiler / bin

Issue with the quartus compilation (with VTXCart c3g version) for the ALTERA MAX3000A EPM3256ATC144-10N, on CHA_CP1, only .

Hi, i have a issue with the Quartus II 13 sp2 on windows 10 compilation for the ALTERA MAX3000A EPM3256ATC144-10N, on CHA_CP1, only .

I use this options : "VTXCart.exe games.txt MVS c3g GenIX PatchMenu GenMAME GenROM" with the c3g option, when i execute VTXCart.exe no have errors, I put the verilog file on "CPLD\MVS\CHA_CP1\rtl\ix_c.inc" I open the quartus proyect "CPLD\MVS\CHA_CP1\synth\cha_cp1.qpf" on quartus, and compile the proyect its make a errors:

Info (12127): Elaborating entity "cp1_top" for the top level hierarchy
Info (278001): Inferred 1 megafunctions from design logic
	Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add0"
Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info (12133): Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
	Info (12134): Parameter "LPM_WIDTH" = "9"
	Info (12134): Parameter "LPM_DIRECTION" = "ADD"
	Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
	Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[1]", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[1]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (280013): Promoted pin-driven signal(s) to global signal
	Info (280014): Promoted clock signal driven by pin "nPORTWEL" to global clock signal
	Info (280015): Promoted clear signal driven by pin "nRESET" to global clear signal
Warning (21074): Design contains 6 input pin(s) that do not drive logic
	Warning (15610): No output dependent on input pin "nPORTWEU"
	Warning (15610): No output dependent on input pin "nROMOEL"
	Warning (15610): No output dependent on input pin "nROMOEU"
	Warning (15610): No output dependent on input pin "nAS"
	Warning (15610): No output dependent on input pin "M68K_RW"
	Warning (15610): No output dependent on input pin "nRESET2"
Info (21057): Implemented 310 device resources after synthesis - the final resource count might be different
	Info (21058): Implemented 30 input pins
	Info (21059): Implemented 40 output pins
	Info (21060): Implemented 24 bidirectional pins
	Info (21063): Implemented 165 macrocells
	Info (21073): Implemented 51 shareable expanders
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 8 warnings
	Info: Peak virtual memory: 4586 megabytes
	Info: Processing ended: Fri Oct 13 01:49:45 2023
	Info: Elapsed time: 00:00:03
	Info: Total CPU time (on all processors): 00:00:03
Info: *******************************************************************
Info: Running Quartus II 64-Bit Fitter
	Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
	Info: Processing started: Fri Oct 13 01:49:46 2023
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off prog_cp1 -c prog_cp1
Info: qfit2_default_script.tcl version: #1
Info: Project  = prog_cp1
Info: Revision = prog_cp1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM3256ATC144-10 for design "prog_cp1"
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|ps[2]~45" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|ps[2]~50" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|gn[2]~5" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[1]~47" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[1]~216" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|genr_node[0]~10" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|gc[1]~10" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|genr_node[0]~15" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|gc[1]~11" of type max_mcell
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~67" of type max_sexp
Error (163105): Cannot route source node "P_ADDR_ALL~38" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[2]~69" of type max_mcell
Error (163105): Cannot route source node "WideOr8~62" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|gs[3]~3" of type max_mcell
Error (163105): Cannot route source node "WideOr8~62" of type max_mcell to destination node "WideOr8~65" of type max_mcell
Error (163105): Cannot route source node "WideOr8~62" of type max_mcell to destination node "lpm_add_sub:Add0|addcore:adder[0]|gn[3]~9" of type max_mcell
Error (163104): Can't place node "P_ADDR_ALL~41" of type max_mcell
Error (163104): Can't place node "P_ADDR_ALL~47" of type max_mcell
Error (163104): Can't place node "P_ADDR_ALL~53" of type max_mcell
Error (163104): Can't place node "WideOr8~81" of type max_mcell
Error (163000): Cannot find fit.
Error: Quartus II 64-Bit Fitter was unsuccessful. 19 errors, 1 warning
	Error: Peak virtual memory: 4729 megabytes
	Error: Processing ended: Fri Oct 13 01:49:49 2023
	Error: Elapsed time: 00:00:03
	Error: Total CPU time (on all processors): 00:00:03
Error (293001): Quartus II Full Compilation was unsuccessful. 21 errors, 9 warnings

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