xuantie-rv / wujian100_open Goto Github PK

@mballackh13
您好，请问一下有MCU的基本信息吗？例如，几级流水线，多少发射，是否支持乱序，FPGA上可综合频率，资源开销等。

如题

wujian100_open 30/105029*100%=0.03%

$ find . -type f | xargs cat | wc -l
105029
$ grep -rn "//" |wc -l
30
$ pwd
~/wujian100_open/soc

$ grep -rn "//" 
sms.v:466:casex ({resp_cfg[3:2], rty_first, resp_cfg[1:0]})  // synopsys parallel_case
sms.v:555:  case (ram_size[2:0])   // synopsys parallel_case
sms.v:557:      case (ram_addr[1:0])   // synopsys parallel_case
sms.v:568:      case (ram_addr[1])     // synopsys parallel_case
common.v:28:  case(clk_sel) // synopsys infer_mux
E902_20191018.v:194:  //  `define HAD_MBKPT_9 
E902_20191018.v:197:    //`define DBG_EXP 
usi0.v:1066:                case({i2cm_hs, i2cm_sbyte}) // synopsys parallel_case
usi0.v:2839:        case(txcnt_bits[4:1]) // synopsys parallel_case
usi0.v:2866:    case(spi_data_size[3:0]) // synopsys parallel_case
usi0.v:2916:        case(txcnt_bits[4:1]) // synopsys parallel_case
usi0.v:2981:        case(cnt_bits[3:0]) // synopsys parallel_case
usi0.v:3071:    case(spi_data_size[3:0]) // synopsys parallel_case
usi0.v:3555:                case(txcnt_bits[2:0]) // synopsys parallel_case
usi0.v:3581:    case(uart_dbit[1:0])  // synopsys parallel_case
usi0.v:3616:        case(uart_pbit[1:0]) // synopsys parallel_case
usi0.v:3669:    case(uart_dbit[1:0]) // synopsys parallel_case
matrix.v:224:// synopsys translate_off
matrix.v:237:// synopsys translate_on
matrix.v:452:// synopsys translate_off
matrix.v:465:// synopsys translate_on
dmac.v:933:    case(data_chnl_cd)  // synopsys parallel_case
dmac.v:957:        //data_chnl_cd[3:0] <= 4'b00 ; 
dmac.v:965:    case(busy_chn_code)  // synopsys parallel_case
dmac.v:986:    case(busy_chn_code)  // synopsys parallel_case
dmac.v:1007:    case(busy_chn_code)  // synopsys parallel_case
dmac.v:1029:    case(busy_chn_code)  // synopsys parallel_case
dmac.v:15707:assign   cntr_blk_decen = ( is_wr_ctrlstt ) & current_rcvvld & (~blk_nu_eql0) ; //& is_blk_src |  
dmac.v:15808:                               //src_single_inten & is_rd_ctrlstt & current_rcvvld   |     
dmac.v:15809:                               //dst_single_inten & is_wr_ctrlstt & current_rcvvld  

rocketchip 3256/45594*100% = 7.14%

$ find . -type f | xargs cat | wc -l
45594
$ grep -rn "//" |wc -l
3256
$ pwd
~/rocket-chip/src

e203 6797/77766*100%=8.74%

$ find . -type f | xargs cat | wc -l
77766
$ grep -rn "//" |wc -l
6797
$ pwd
~/e200_opensource/rtl/e203

关于USI FIFO 中断， 文档上的RX_FIFO_TH是3bit，设定值为1~7Byte。

但是，RTL上只有2个bit, 设定值也不一样。

请问SOC相关的verilog代码在移植到vivado后需要自己配置ip核吗，还是说有现成的使用呢？

RT

这里语法是说英语语法，README.md满是语法错误，貌似头一句就挂了。如果要走向世界，是不是改改。

为什么我用vivado2019.1综合后时序不对，请问大家怎么解决这个问题

那个钉钉wujian100的讨论区二维码已经过期啦，可以再给一个新的吗？

看了XC7A——FPGA开发板用户手册v1.0。文档感觉主要讲的是一些软件方面，还有一些简单的硬件连接关系。因为想借助这个平台，在FPGA上做一些有意思的电路，应用在比如边缘计算领域。能不能在今后的项目更新中更新如下内容
1. 整个开发板的原理图，以及PCB文件。
2.在用户手册更新中单列一章，简要说明一下wujian100的架构，提供一些系统的简要框图。
3.在用户手册粗劣说明一下两个stm32的主要工作流程。能否顺便将stm32的源程序开源出来。
4.在用户手册中说明一下板载资源，以及主要用处。

项目里用的shell是csh，但大部分的Linux发行版都是bash，不带csh。用 chsh 切换默认shell后，还会有各种问题。如果需要bash支持，我就开个pr. @mballackh13

我想知道，现在申请开发板试用，能用多长时间？如果购买的话多少钱

请问有没有关于e902代码命名规则，module 命名规范的文件，方便理解、阅读，在没有注释的情况下看代码真的太难了

您好，

我按照这个路径： https://www.t-head.cn/product/mcu-platform?spm=a2ouz.12987052.0.0.167548abiiSAQs下载了riscv的工具包。

我使用的工具包是：riscv64-elf-x86_64-20190731.tar.gz。

但在运行'../tools/run_case -sim_tool vcs ../case/timer/timer_test.c'室，它报出了异常：
Fatal error：invalid -march= option：`rv32emcxcki'

我应该如何处理呢？

谢谢。

代码都没有注释，没有设计文档很难看懂

如何获得在线调试器工具

https://github.com/SymbiFlow/yosys

WARNING: File inst.pat referenced on E:/RiscV/wujian100/wujian100/wujian100.srcs/sim_1/imports/tb/tb.v at line 256 cannot be opened for reading. Please ensure that this file is available in the current working directory.
######time: 0, Dump start######
START TO LOAD PROGRAM

WARNING: File data.pat referenced on E:/RiscV/wujian100/wujian100/wujian100.srcs/sim_1/imports/tb/tb.v at line 275 cannot be opened for reading. Please ensure that this file is available in the current working directory.
run: Time (s): cpu = 00:00:08 ; elapsed = 00:00:38 . Memory (MB): peak = 1899.332 ; gain = 0.000

As the problems showed in the quotes， how can I get the files inst.pat and data.pat?

The interface port of E902_20191018 is so many, but lack of any document about it.

There r several issues about the readme file, please update relative information.

1. the download link of riscv toolchain/debug tool/IDE is not accurate or out of date.
2. setup.csh not support csh shell, there is a need of sh configuration script.
3. the QR code of Dingtalk is out of date.

No comments on the SOC codes. Is that on purpose?

In apb0_params. v

Error: Verilog 2000 keyword parameter used in incorrect context
Please tell me why and how to solve this.

The core E902_20191018.v appears to be generated code, with no way to modify it. This will be an issue for it's more wider adoption.

Ideally the original source and the tools to regenerate the verilog would be included in this repository.

there is a RTL bug in /soc/gpio.v line 344 . It caused CPU can not clear GPIO interrupt
//code// if(paddr[`GPIO_ADDR_LHS:2] == GPIO_INT_LEVEL_SYNC_OFFSET)

suggetion:
//code// if(paddr[`GPIO_ADDR_LHS:2] == GPIO_INT_CLR_OFFSET )

I can't find the link on web. please notice me,thanks!

https://www.t-head.cn/product/mcu-platform?spm=a2ouz.12987052.0.0.167548abiiSAQs

请问钉钉群现在是不能加入了吗

因为 wujian100 使用 E902 cpu core，看 E902 手册，里面有平头哥的扩展指令。
从平头哥网站上下载的工具链只有二进制，没有源码。

请问哪里有平头哥适配过的工具链的源码？

page14

CoreTim int id should be 7

这个寄存器的值有点问题吧，从代码逻辑看，应该上面是0x1，下面是0x0吧？

Synplify Pro J-2015.03
Vivado 2017.4

ERROR: [DRC RTSTAT-6] Partial route conflicts: 746 net(s) have a partial conflict. The problem bus(es) and/or net(s) are x_cpu_top/CPU/x_cr_had_top/A15d/A13e[0], x_cpu_top/CPU/x_cr_had_top/A15d/A13e[3], x_cpu_top/CPU/x_cr_had_top/A15d/A13e[6], x_cpu_top/CPU/x_cr_had_top/A15d/A13e[12], x_cpu_top/CPU/x_cr_had_top/A18545/A91, x_cpu_top/CPU/x_cr_had_top/A18545/A145[9], x_cpu_top/CPU/x_cr_had_top/A18545/A145[19], x_cpu_top/CPU/x_cr_had_top/A18545/A146[2], x_cpu_top/CPU/x_cr_had_top/A18545/A147[12], x_cpu_top/CPU/x_cr_had_top/A18545/A147[27], x_cpu_top/CPU/x_cr_had_top/A18545/A147[30], x_cpu_top/CPU/x_cr_had_top/A18545/A148[5], x_cpu_top/CPU/x_cr_had_top/A18545/A1855b[5], x_cpu_top/CPU/x_cr_had_top/A18545/A1855b[7], x_cpu_top/CPU/x_cr_had_top/A18545/A1861c[4:0]... and (the first 15 of 738 listed).

Hi wujian100 owners, thanks for your contribution to open the source code of wujian.
But I met some trouble when I want to know more about its architecture or details inside.
Could you release some document like instruction set(ISA) and illustration of module level inside it ?
It looks like a user guide for software engineers more than for hardware engineers in the folder of doc.

1.为什么CDK只有Windows版本？
2.不用synplify只用vivado可不可以？synplify实在是弄不到软件和license
3.source setup,csh的时候一直报语法错误，不太懂这个，请问怎么解决呢？报错如下
syntax error near unexpected token '('

riscv64-unknown-elf-gcc: error: The ISA name 'xcki' is no longer maintained, please use 'xthead{c,e,se}' instead

Firtly, Thanks for T-HEAD team, I have got the amazing FPGA board! :)
It's very easy to kickstart with the help of user guide....
Got only one problem, the provided driver of CSKY Debug Server is based on libusb-win32! :(
libusb-win32 is very yesterday, not supported well by win8/win10 (signature), libusb-win32 now is replaced by libusb1.0 (which also support winusb).
So I generate a new libusbK based driver package by LibusbK -> Driver install Creator Wizard
It drives ck-link work well under windows 10

LibusbK package: https://sourceforge.net/projects/libusbk/
You can also use Zadig: https://zadig.akeo.ie

fail to scan by wechat

我使用自己的FPGA板
想用CDK進行調試
但是沒有CKLINK
請問CDK能支援其他相同openOCD的JTAG嗎？

在setup.csh 中需要手动配置 vcs等仿真环境，vcs作为一种商业软件不符合开源社区精神
建议使用iverilog+gtkwave作为仿真环境。
如果issues通过，稍后可提交pull requests。

wujian100_open_fpga_top.v 文件内部只有接口描述，没有内部逻辑实现么？很少看到大厂的verilog代码：）希望能开源一些观摩下～另外请问现在平头哥的fpga产品相当于altera哪条产品线上的产品呢？总之，感谢开源，希望看到更多verilog和vhdl代码

如果能用10ping的jtag替代的话，pin脚应该怎么连

原理图上的D6那个防防范接的二极管在板子上没有，怀疑提供原理图和板子不对应，不知道其他位置有没有不对应的地方，建议更新一下原理图