Kovan SD Project

FPGA and server files for Kovan-based SD tap board

Pin Mapping (LCD header)

The following is a mapping of pins from the tap board to the FPGA's LCD header:

DA LCD_R7 DB LCD_R6 DC LCD_R5 DD LCD_R4 DE LCD_R3 DF LCD_R2 DG LCD_G7 DH LCD_G6

ALE LCD_G5 CLE LCD_G4 WE LCD_G3 CS LCD_G2 RE LCD_B7 RB LCD_B6 UK0 LCD_B5 UK1 LCD_B4

UK2 LCD_B3 UK3 LCDO_VSYNC UK4 LCDO_HSYNC UK5 LCDO_DEN UK6 LCDO_DOTCLK UK8 LCDO_RESET_N

Pin Mapping (HDMI connector)

The following is a mapping of pins from the tap board to the FPGA's HDMI header:

UK7 UK7_BUF UK9 UK9_BUF SD_CS SD_SCLK SD_TURNON SD_DAT1 SD_DAT1 SD_DI SD_DO SD_CD

Pin Mapping (FPGA as passthrough)

When the FPGA firmware is loaded, the followng pins pass directly through:

CAM_VSYNC SD_SCLK CAM_HSYNC SD_MOSI CAM_VCLKO SD_CS CAM_PCLKI SD_TURNON CAM_MCLKO D_NEXT # Input, toggle to present new data on pins CAM_D0 NAND_DA CAM_D1 NAND_DB CAM_D2 NAND_DC CAM_D3 NAND_DD CAM_D4 NAND_DE CAM_D5 NAND_DF CAM_D6 NAND_DG CAM_D7 NAND_DH

LCD_R0 D_READY # Output, toggles when data is present on pins LCD_R1 D_AVAIL # Output, goes high when new data is available LCD_R2 SD_MISO LCD_R3 NAND_CLE LCD_R4 NAND_ALE LCD_R5 NAND_CE LCD_G0 NAND_WE LCD_G1 NAND_RE LCD_G2 LED_TIMER[0] LCD_G3 LED_TIMER[1] LCD_G4 LED_TIMER[2] LCD_G5 LED_TIMER[3] LCD_B0 LED_TIMER[4] LCD_B1 LED_TIMER[5] LCD_B2 LED_TIMER[6] LCD_B3 LED_TIMER[7] LCD_B4 LED_TIMER[8] LCD_B5 LED_TIMER[9] LCD_SUPP0 LED_TIMER[10] LCD_SUPP1 LED_TIMER[11] LCD_SUPP2 LED_TIMER[12] LCD_SUPP3 LED_TIMER[13] LCD_SUPP4 LED_TIMER[14] LCD_SUPP5 LED_TIMER[15]

I2S_DI0 I2S_DO0 I2S_LRCLK0 I2S_CDCLK0 I2S_CLK0

FPGA_MISO FPGA_MOSI FPGA_SYNC FPGA_DIN FPGA_CCLK PWR_SCL PWR_SDA Xi2cSDA Xi2cSCL

Programming Model

Every time the WE or RE pin rises, the FPGA captures the values present on DA-DH, whether it was a read or a write, and whether it was a command, address, or data. Additionally, a 26-bit timestamp will be captured, along with 10 bits of the "unknown" data pins.

When data is available, the D_AVAIL pin goes high. When the data buffer is empty, D_AVAIL returns low.

In order to read data, toggle D_NEXT. The FPGA will load the new values onto the output pins, and will toggle D_READY when it has done so. When D_READY equals D_NEXT, then the data may be read. Note that if you attempt to read data when D_AVAIL is low, then the output will be read as zero.