xilinx / rfsoc-pynq Goto Github PK

Hi,

Thank you for creating a Python interface for the RFSoC platform. It is very beneficial for researchers who are not familiar with lower-level logic to conduct RF experiments. We have been looking into this and are wondering how to obtain an RFSoC board from Xilinx for academic use. We have submitted purchase requests (through [email protected]) to the XUP (Xilinx University Program) following the guidelines indicated on Xilinx's official purchasing page; however, we haven't received any response yet. Do you know of any other ways to contact them besides sending an email to [email protected]?

First and foremost, thanks for this great platform (RFSoc4x2) and framework (PYNQ)!

While running some tests (base overlay), I came across the software-enforced maximum transaction length of 32768 samples per DMA transfer (i.e. base.radio.receiver.channel[i].transfer(number_samples)), which is quite limiting considering that the PS has 4GB of DRAM and the frontend samples at rates of up to 5GSPS, which leads to a capture window of 6.6.ms (considering DDC bypass).

I first though that this is a Xilinx DMA IP limitation (as 2^15=32768), but I figured out that the block is actually configured for transfer lengths of up to 2^26 (see screenshot below, for the current master of this repo).

Furthermore, removing the software input checking leads to successful transfers up to 37000 (log2(37000) not an integer), with a failure at 38000. Is there an easy way of lifting this limitation and offer transfer lengths at least up to 4GB length? I couldn't figure out so far why it stops working at 38000 samples, since the packet generator uses 32bit integer fields (Packet_Generator.vhd#L58), and thus should be able to have transfer lengths of 2^31.

Any hints towards this matter would be appreciated.

Hi there!

First of all, I wanna congratulate and thank you for your great work.

I am developing with the ZCU111 and I have one question. For the boards RFSoC2x2, RFSoC4x2 and ZCU208 I have found the base overlay on which I can do some modifications like insert my own blocks IP into the PL for stimulate the DAC but not in the ZCU111.

Have any base overlay compatible with ZCU111? RFSoC2x2 base overlay maybe?

Many thanks again, best regards,
Jorge

Hi,
I came across this repo and found that there is currently no support for the ZCU216 board.
Do you plan to support ZCU216 board in the near future?

Hello,

I want to build this project to test with pynq but is not possible since the project include a purchase ip core:

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
base_i/OffloadEngine/xxv_ethernet_0/inst/i_base_xxv_ethernet_0_0_top_0/i_base_xxv_ethernet_0_0_CORE ()
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

the 25G/10G Ethernet MAC+PCS/PMA is a purchase option not available for most user is not possible to modify this project.

https://www.xilinx.com/products/intellectual-property/ef-di-25gemac/ef-di-25gemac-order.html

could you provide a version without this IP core?.

Hello again,

in vivado base project for zcu208 evaluation board I discover the user_sysref_adc and user_sysref_dac are not connected so it's not possible to evaluate the multi-tile-sync with this project besides the ip core is configured to do it,

and since also I can't modify this project since I can't compile it and test it like expressed in other issue

#12

Since the build TCL scripts are specific to a particular vivado version, having the 'vivado' command hard-coded in makefiles can create problems if you have multiple installed versions.

Example from <base>/boards/RFSoC4x2/base/Makefile

...
block_design:
	vivado -mode batch -source $(overlay_name).tcl -notrace
...

Suggest changing this to a macro so it can be passed during the top-level make all command

# set command to use command line or shell export, or default
VIVADO := $(if $(VIVADO),$(VIVADO), vivado) 
...
block_design:
	${VIVADO} -mode batch -source $(overlay_name).tcl -notrace
...

Now the command can be called with any version you wish by override
make -DVIVADO=/tools/Xilinx/Vivado/2022.1/bin/vivado all
or

export VIVADO=/tools/Xilinx/Vivado/2022.1/bin/vivado
make all