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As title, current lowest is 2.

This would require a different port config to happen.

I've noticed a delay of 1 sample between the left and the right channel using the i2s-master and the loopback-demo on SliceKit. The left channel is 1 sample behind the right channel. The measure was taken with an analogue oscilloscope and the delay was around 21µs @48khz. Switching to 96kHz, the delay was around 10.5µs. Unfortunatelly i'm not able to proof it with a logic analyser.

Due to declaration of arrays of size 0

Since the method i2c_master_read_reg() has been removed from the latest version module_i2c_single_port, the CODEC device ID doesn't work anymore.

Probably a die on receipt of a control token (instead of data) would work best.

Assuming Left is Channel_0 and Right is Channel_1.
A test AIF file was prepared with white-noise on the left channel, and speech on the right channel.

The AIF file was played using Amarok, and when listened to directly (using headphones connected to the PC) the tests signals appear on the correct channels.

Then the app_slicekit_vocoder application (from sw_audio_effects) was tested.
The audio from the PC headphone socket was fed into Channel_0 and Channel_1 of the Audio-Slice.
In the S/W, as soon as the input was received from (sc_i2s) it was captured using xSCOPE.
The xscope trace clearly show that left and right channels are swapped. i.e. the white noise is now on channel_1(right)

1 sample delay between DAC and ADC data

Currently doesn't build.

Could also support Left Justified/Right Justified.