wuxx / icesugar-pro Goto Github PK

iCESugar series FPGA dev board

Makefile 0.56% Verilog 97.84% C++ 1.11% Shell 0.49%

icesugar-pro's Introduction

iCESugar-pro

iCESugar-pro
Hardware
- ECP5
- SDRAM
- SPI-Flash
- Clock
- Peripheral
- JTAG
- iCELink
virtual-machine-image
How-to-setup
How-to-buy
Copyright Statement
Reference

iCESugar-pro

iCESugar-pro is a FPGA board base on Lattice LFE5U-25F-6BG256C, which is fully supported by the open source toolchain (yosys & nextpnr), the board is designed in DDR2 SODIMM form with 106 usable IOs, with on-board 32MB SDRAM, it can run RISC-V Linux. the on board debugger iCELink (base on ARM Mbed DAPLink) support drag-and-drop program, you can just drag the FPGA bitstream into the virtual disk to program, and with a additional USB CDC serial port direct connect to FPGA, so you can only use one TYPE-C cable to develop and test.

Hardware

ECP5

LFE5U-25F-6BG256C (BGA256 0.8mm pitch)

LUTs: 24K
sysMEM Blocks: 18Kb x 56
Embedded Memory: 1008Kb
Distributed RAM bits: 194Kb
18 x 18 Multipliers: 28
PLL x 1

SDRAM

SDRAM use IS42S16160B (32MB)

SPI-Flash

SPI Flash use W25Q256JV (32MB)

Clock

a 25MHz crystal is connect to P6

Peripheral

a RGB LED is connected to {A11, A12, B11}
a SDCARD slot, support SPI/SDIO
106 usable IOs out with SODIMM-DDR2-200P, can use with ext-board.

JTAG

the native JTAG of ECP5 is connect to the on-board iCELink, you can flash bistream with this JTAG interface (called JTAG1). and there is also another JTAG interface (actually just some GPIOs of ECP5) connect to the iCELink too (called JTAG2), if you design a SoC with a JTAG interface support, then you can use the JTAG2 to debug your SoC. only one JTAG work a one moment. so use the icesprog tool with command icesprog -j 1 or 2 to switch between these two JTAG interface.

$icesprog -j 1
JTAG --> [JTAG-1]
         [JTAG-1]
         TCK:  iCELink-PB6  -- ECP5-JTAG-TCK (25F-BG256-T10)
         TMS:  iCELink-PB4  -- ECP5-JTAG-TMS (25F-BG256-T11)
         TDI:  iCELink-PB5  -- ECP5-JTAG-TDI (25F-BG256-R11)
         TDO:  iCELink-PB3  -- ECP5-JTAG-TDO (25F-BG256-M10)

         [JTAG-2]
         TCK:  iCELink-PA14 -- ECP5-IO-PL8D  (25F-BG256-F5)
         TMS:  iCELink-PA13 -- ECP5-IO-PL17A (25F-BG256-H5)
         TDI:  iCELink-PA0  -- ECP5-IO-PL38A (25F-BG256-N4)
         TDO:  iCELink-PA1  -- ECP5-IO-PL17D (25F-BG256-J5)

done

iCELink

iCESugar-pro has a on board debugger named iCELink (base on APM32F1)，you can only use one USB wire to program the FPGA and debug, here is detail:

drag-and-drop program, just drop the bitstream into the virtual USB DISK iCELink, then wait a few second, the iCELink firmware will do the total program work
USB CDC serial port, it can use to communicate with FPGA
2 JTAG interfaces for flash the ECP5 or debug the SoC on ECP5
use the command tool icesprog to flash or do more config, here is the help info

$icesprog -h
usage: /home/pi/oss/icesugar/tools/icesprog.arm [OPTION] [FILE]
             -w | --write                   write spi-flash or gpio
             -r | --read                    read  spi-flash or gpio
             -e | --erase                   erase spi-flash
             -p | --probe                   probe spi-flash
             -o | --offset                  spi-flash offset
             -l | --len                     len of write/read
             -g | --gpio                    icelink gpio write/read
             -m | --mode                    icelink gpio mode
             -j | --jtag-sel                jtag interface select (1 or 2)
             -c | --clk-sel                 clk source select (1 to 4)
             -h | --help                    display help info

             -- version 1.1a --

Tips

cause the iCELink connect some GPIOs to the ECP5, you can control this GPIOs with icesprog to do some self defined behavior, for example, to control the iCELink-PA14 -- ECP5-F5 line out low, type these command.

$icesprog -g PA14 -m out
$icesprog -g PA14 -w 0

How-To-Program

there are multiple ways to program the bitstream.

drag-and-drop program, this may be the fastest and simplest way to flash.
use the command icesprog xxx.bit, this can provide more configable parameters.
use the command dapprog xxx.bit (program to flash) or dapprog xxx.svf (program to SRAM)
the icesprog binary and source code is in icesugar repo, and the dapprog is a bash wrapper of openocd command, click here to check how to setup.

virtual-machine-image

link：https://pan.baidu.com/s/1vV2ckFpOuyd600Y47Tl1sw
verify code：i3en
user: ubuntu
passwd: ubuntu
or https://mega.nz/file/uvJTWKrK#1bBgBkJPZrszwHQSTHHL-RLjxGIru0Qv0qUgmULZZVs

the env include yosys, nextpnr, icestorm, gcc, sbt.

How-to-setup-env

Linux

recommend use the virtual machine, it simple and convenient
FPGA toolchain reference icestorm
gcc toolchain reference riscv-gnu-toolchain
Alternatively, you can download the pre-built toolchain provided by xPack or SiFive

https://xpack.github.io/riscv-none-embed-gcc/install/
https://www.sifive.com/software icesprog is command tool for iCESugar program，it depend libusb and hidapi
$sudo apt-get install libhidapi-dev
$sudo apt-get install libusb-1.0-0-dev

Windows

now you can use the msys2 environment to setup the open source toolchain easily, download msys2 install executable here, install it, then open the msys2 mingw terminal (search msys2 in windows start menu)

#pacman -Syu
#pacman -S mingw-w64-x86_64-eda

select the yosys, nextpnr, icestorm, icesprog and install, after installed, everything is same as in linux!

How-to-buy

you can buy iCESugar-pro and PMOD peripherals from our offcial aliexpress shop Muse Lab Factory Store or search iCESugar-Pro FPGA on www.aliexpress.com

Copyright Statement

the hdmi test verilog source code is from https://github.com/DoctorWkt/ULX3S-Blinky
the linux related project is from https://github.com/litex-hub/linux-on-litex-vexriscv
for hobby and personal usage, you are free to use the iCESugar-pro, you can also make the board yourself by document & firmware in this repo.
for the commercial usage, if you got iCESugar-pro Board from our official shop and use in other commercial product, that's no problem, in other situation, please contact us in advance.

Reference

icesugar-pro's People

Contributors

Stargazers

Watchers

icesugar-pro's Issues

FPGA pin error when connecting SPI-Flash

Can FPGA in icesugar-pro communicates with SPI-Flash and get data stored inside? I want to put some binary code inside to let FPGA execute it.
According to the schematic pdf, I set lpf file as below:

# SPI-FLASH
LOCATE COMP "flash_cs"   SITE "N8";
LOCATE COMP "flash_mosi" SITE "T8";
LOCATE COMP "flash_miso" SITE "T7";
LOCATE COMP "flash_io2"  SITE "M7";
LOCATE COMP "flash_io3"  SITE "N7";
LOCATE COMP "flash_clk"  SITE "N9";

IOBUF PORT "flash_cs"   IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_clk"  IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_mosi" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_miso" IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_io2"  IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "flash_io3"  IO_TYPE=LVCMOS33 DRIVE=4;

However when compiling with nextpnr-ecp5:

nextpnr-ecp5 --25k --package CABGA256 --speed 6 --json top.json --textcfg top_out.config --lpf top.lpf

it will report error of:

ERROR: IO pin 'flash_clk$tr_io' constrained to pin 'N9', which does not exist for package 'CABGA256'.
ERROR: Packing design failed.

Is there any problem with this setting?

Pin Error G5 -> G4

Hello,

I have identified a pin error where the SO-DIMM pin 144 is not G5 as listed in the markdown table but is G4. The schematic pdf is correct in this case.

I have checked this on real hardware. There may be more errors, I have not checked every pin in the table and the schematic.

Thanks

Wrong programming command on example Makefiles.

Hello,

Issue Description:

I attempted to implement the command referenced in the example Makefiles for programming the IceSugar-Pro development board. Unfortunately, the provided command does not work as expected.

Solution Reference:

The solution to this issue is documented in a related issue that I opened in the openFPGALoader repository: trabucayre/openFPGALoader#398.

Suggested Command Change:

I propose updating the Makefiles in the examples to use the following command:
Instead of:

openFPGALoader -c digilent_hs2 $(TARGET).bit

Use:

openFPGALoader -c cmsisdap --vid=0x1d50 --pid=0x602b $(TARGET).bit

This change resolved the issue for me and should work better with the IceSugar-Pro development board.

Question on Vendor ID and Product ID:

Additionally, I have a question: Are the vendor ID and product ID always the same for all IceSugar-Pro boards? It would be helpful to clarify whether these values are consistent across all devices.

Thank you for your attention to this matter.

iCELink open fail!

I have ICESugar Pro 1.3 with colourlight expansion board.

I installed icesprog to read/write to the fpga. at first this was working. and now this doesnt work anymore and says "iCELink open fail!"

I can drag and drop bit stream files on to the drive to program. However, I would like to debug also with the usb on the expansion board:

Linux don't works

Hi.
I load latex_no_dram.bit and it works. All others does not works. This is memory problems?
I have icesugar-pro 1.3 from ali.

iCELink open fail!

Not clear how to use this board. I got it two days ago, and still can't confirm if it works or not.

$ uname -a
Linux ubu 5.15.0-56-generic #62-Ubuntu SMP Tue Nov 22 19:54:14 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux

$ icesprog -j 1
iCELink open fail!

$ lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 003: ID 0e0f:0002 VMware, Inc. Virtual USB Hub
Bus 002 Device 002: ID 0e0f:0003 VMware, Inc. Virtual Mouse
Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub

$ sudo dmesg  | grep USB | grep Link
[   18.979544] hid-generic 0003:0D28:0204.0002: hiddev0,hidraw1: USB HID v1.00 Device [ARM DAPLink CMSIS-DAP] on usb-0000:02:00.0-2.1/input3
[  244.862760] hid-generic 0003:0D28:0204.0003: hiddev0,hidraw1: USB HID v1.00 Device [ARM DAPLink CMSIS-DAP] on usb-0000:02:00.0-2.1/input3
[  642.419705] hid-generic 0003:1D50:602B.0004: hiddev0,hidraw1: USB HID v1.00 Device [MuseLab DAPLink CMSIS-DAP] on usb-0000:02:00.0-2.1/input3

$ icesprog
/home/valery/oss-cad-suite/libexec/icesprog: unrecognized option '--version'
usage: /home/valery/oss-cad-suite/libexec/icesprog [OPTION] [FILE]
             -w | --write                   write spi-flash or gpio                      
             -r | --read                    read  spi-flash or gpio                      
             -e | --erase                   erase spi-flash                              
             -p | --probe                   probe spi-flash                              
             -o | --offset                  spi-flash offset                  	 
             -l | --len                     len of write/read                            
             -g | --gpio                    icelink gpio write/read                      
             -m | --mode                    icelink gpio mode                            
             -j | --jtag-sel                jtag interface select (1 or 2)               
             -c | --clk-sel                 clk source select (1 to 4)                   
             -h | --help                    display help info                            

             -- version 1.1b

$ iceprog
iceprog: missing argument
Try `/home/valery/oss-cad-suite/libexec/iceprog --help' for more information.

Could you support the board with nmigen?

I am new to this domain (open hardware and nmigen).
I am trying to do an example blinky in nmigen and try to make it build the bitstream file for FPGA.
Here is my current example code.

import os
import subprocess
from typing import List
from nmigen import Elaboratable, Module, Signal
from nmigen.build import *
from nmigen.build.run import LocalBuildProducts
from nmigen.cli import main_parser, main_runner
from nmigen.vendor.lattice_ecp5 import *

class Blinker(Elaboratable):
    def __init__(self):
        pass
    def elaborate(self, platform: Platform) -> Module:
        led   = platform.request("led", 0)
        timer = Signal(20)

        m = Module()
        m.d.sync += timer.eq(timer + 1)
        m.d.comb += led.o.eq(timer[-1])
        return m
    
    def ports(self) -> List[Signal]:
        return []

class Board(LatticeECP5Platform):
    device = "LFE5U-25F"
    package = "BG256"
    speed = "6"
    default_clk = "clk1"
    default_rst = "rst"
    resources = [
        Resource("clk1", 0, Pins("P6",dir="i"), Clock(25e6),
            Attrs(IO_TYPE = "LVCMOS33")),
        Resource("rst", 0, Pins("L14",dir="i"),
            Attrs(IO_TYPE = "LVCMOS33")),
        Resource("led", 0, Pins("B11",dir="o"),
            Attrs(IO_TYPE = "LVCMOS33")),
    ]
    connectors = []
    def toolchain_program(self, products, name):  
        iceprog = os.environ.get("ICEPROG", "iceprog")
        with products.extract("{}.bin".format(name)) as bitstream_filename:
            subprocess.check_call([iceprog, bitstream_filename])
if __name__ == "__main__":
    Board().build(Blinker(), do_program= False)

But not sure if it works.. my board is not here yet.
Can you support a board file for nmigen? It would be nice!
Or maybe a blinky example? That would be wonderful!

Thank you

Missing LICENSE

Can LICENSE be added so people know how the code can be handled?

VM Links both broken

The Chinese and Mega link are both not available, at least not to non Chinese.

Getting junk in terminal with linux-litex configuration

I'm macOS user and using minicom as uart-terminal(I've used in other case - everything was fine in other cases, configuring FPGA messages are fine).

But when I've tried linux litex I've got this

Port speed as specified in readme file.
Is there issue cause configuration was ported from other board where clock was different?

It isn't most important thing for this board but I'd like check samples.

P.S. thank you for your boards. I have iCESugar 1.5 and Pro(now) both and they're great for me

Slow upload via onboard iCELink

Currently FPGA upload takes 10x more than synthesis (both DAPlink & file copy mode).
Is there any way to improve speed? Is firmware of your iCELink opensource so that one can try to improve the speed, probably by implementing some other faster protocol?

In the worst case, is it possible to connect external programmer to achieve faster upload speeds?

Review your way to distribute the software

25GB snapshot from the extremely slow site with the Chinese language it is the nightmare.

SDRAM read/write example

hi, is there any SDRAM read/write example? thanks

你有 LVDS 输入支持吗？

你好，我想知道你是如何提供对这个板子中的LVDS摄像头接口的支持的。有什么我可以开始的例子吗？

Is this board support diamond?

Is this board support diamond? I got

unable to build blink

3.51. Executing JSON backend.
ERROR: Module rst_gen contains processes, which are not supported by JSON backend (run proc first).
make: *** [Makefile:9: blink.json] Error 1

thanks
Peter

JTAG DR scan chain is empty

Hello!

I tried to scan JTAG chain using ecpdap and got the error:

> ecpdap scan
2022-05-14T00:47:21.773Z ERROR jtagdap::jtag > JTAG DR scan chain is empty
Error: JTAG scan chain broken: check connection or try a larger --scan-chain-length.

If to use openocd:

>  openocd -f cmsisdap.cfg -c \
    "   init;
        scan_chain;
        exit;
    "

Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'adapter speed' not 'adapter_khz'
Info : CMSIS-DAP: SWD  Supported
Info : CMSIS-DAP: JTAG Supported
Info : CMSIS-DAP: FW Version = 0254
Info : CMSIS-DAP: Serial# = 07000001003500263700000c4e504332a5a5a5a597969908
Info : CMSIS-DAP: Interface Initialised (JTAG)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : High speed (adapter speed 10000) may be limited by adapter firmware.
Info : clock speed 10000 kHz
Info : cmsis-dap JTAG TLR_RESET
Info : cmsis-dap JTAG TLR_RESET
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: ecp5.tap: IR capture error; saw 0xff not 0x1
Info : cmsis-dap JTAG TLR_RESET
Warn : Bypassing JTAG setup events due to errors
Warn : gdb services need one or more targets defined

These errors are raised only if to connect usb to the ext-board. If to connect directly to icesugar pro, all is okay.

TDO check error at line 10

I am trying to flash a simple nand project to my icesugar-pro with ext board using the USB-C DAPLink programmer.

I have successfully compiled openocd and added dapprog in my user PATH variable.

but when I try to flash using dapprog, it gets a TDO error:

$ dapprog top.bit                          
EXT: bit
TARGET: top_flash.svf
[sudo] senha para chandler: 
Open On-Chip Debugger 0.12.0-rc2+dev-00962-g12ce17094 (2022-10-28-13:16)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'adapter speed' not 'adapter_khz'
Info : CMSIS-DAP: SWD supported
Info : CMSIS-DAP: JTAG supported
Info : CMSIS-DAP: Atomic commands supported
Info : CMSIS-DAP: FW Version = 0254
Info : CMSIS-DAP: Serial# = 07000001002400614d0000164e514137a5a5a5a597969908
Info : CMSIS-DAP: Interface Initialised (JTAG)
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 10000 kHz
Info : cmsis-dap JTAG TLR_RESET
Info : cmsis-dap JTAG TLR_RESET
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: ecp5.tap: IR capture error; saw 0xff not 0x1
Info : cmsis-dap JTAG TLR_RESET
Warn : Bypassing JTAG setup events due to errors
Warn : gdb services need one or more targets defined
svf processing file: "top_flash.svf"
5%    Info : cmsis-dap JTAG TLR_RESET
Info : cmsis-dap JTAG TLR_RESET
Info : cmsis-dap JTAG TLR_RESET
Error: tdo check error at line 10
Error:     READ = 0xffffffff
Error:     WANT = 0x41111043
Error:     MASK = 0xffffffff
Error: fail to run command at line 2137
Error: tdo check error at line 10
Error:     READ = 0xffffffff
Error:     WANT = 0x41111043
Error:     MASK = 0xffffffff
Time used: 0m7s818ms 
svf file programmed failed

I have tried also to drag and drop the bitstream file to DAPLINK in File Manager, I tried also to flash using icesprog but nothing seems to be working.

I actually see the red led blinking from DAP chip in ext board when a run the flash program, but the FPGA itself remains with the older project.

Can someone help me?

Thanks in advance!

DDR vs DDR2

I believe that this board is compatible with the SODIMM-DDR2-200P socket, not DDR as mentioned in the README.md

where is the command icesprog

Hi, where is the command icesprog ?

Best way to provide power

Curious to know how everyone is providing power to the icesugar-pro. When connected to USB-C on the board itself, USB power becomes the 5V line to power everything. If you are designing another board that the IS-pro plugs into that provides its own 5V, you now have competing 5V sources if you leave the USB-C connected to a computer (for programming). I didn't want to use barrier diodes due to the voltage drop so decided to use a short USB-A to USB-C connector that provides the baseboard 5V when plugged in, and to use the USB/computer power to power everything when programming. I don't like the extra cable requirement, but it does work. I considered voltage selectors, but those would really need to be on IS-pro board itself and choose a voltage source from the USB-C or from an unused pin(s) on the SODIMM pins used as an input.

Links to prebuilded images don't works

Hi.
I suggest than some links to baidu and mega.nz does not works. I try to install linux enveronment with source code by instruction from https://waxpple.github.io/posts/day11/ but this instruction also dont works. Can you create step-by-step instruction for newbies for create working enveronment in which I can compile bitstream from python and verilog sources. Thanks.

porting riscv

hi, any tutorial to port vexcore risc-v to this board? thx

unable to find CMSIS-DAP device

Hi
Any hints?

/home/peter/workspace/icesugar-pro/src/blink>../../tools/dapprog  blink.bit
EXT: bit
TARGET: blink_flash.svf
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Error: unable to find CMSIS-DAP device

thanks

wuxx / icesugar-pro Goto Github PK

icesugar-pro's Introduction

iCESugar-pro

iCESugar-pro

Hardware

ECP5

SDRAM

SPI-Flash

Clock

Peripheral

JTAG

iCELink

Tips

How-To-Program

virtual-machine-image

How-to-setup-env

Linux

Windows

How-to-buy

Copyright Statement

Reference

Colorlight-FPGA-Projects

icestorm toolchain

riscv gcc toolchain

iCESugar

iCESugar-nano

Examples

SpinalHDL

icesugar-pro's People

Contributors

Stargazers

Watchers

Forkers

icesugar-pro's Issues

Issue Description:

Solution Reference:

Suggested Command Change:

Question on Vendor ID and Product ID:

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