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penglib's Issues

verdor memory io default value

  • TEST1A/B should be set to False when we work on normal mode
  • There is only LS input instead of LSA or LSB
  • RME setting can be set to False as default, let the SRAM choose internal default RM setting.
  • DA and QB as data input and output interface.

memory enable assignment

PhaseSramConverter.scala:

          ram.io.clka := wr.clockDomain.readClockWire
          ram.io.apa.addr.assignFrom(wr.address)
          ram.io.apa.cs.assignFrom(wr.clockDomain.isClockEnableActive && wrapBool(wr.writeEnable))
          ram.io.dp.we.assignFrom(wrapBool(wr.writeEnable))
          ram.io.dp.din.assignFrom(wr.data)

          ram.io.clkb := rd.clockDomain.readClockWire
          ram.io.apb.addr.assignFrom(rd.address)
          ram.io.apb.cs.assignFrom(rd.clockDomain.isClockEnableActive && wrapBool(rd.readEnable))
          wrapConsumers(rd, ram.io.dp.dout)

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