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erikik8090 avatar idoheinemann avatar savioor avatar shooshx avatar

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corewars-risc-v's Issues

Change to RISC-V memory model

We are currently using the x8086 memory model, and just using the arena segment.
Need to change it to the RISC-V memory model.

`sw x1, 128(x2)` unexpected behavior

Courtesy of @Savioor at shooshx#11
This command should write the contents of x1 into the address that comes 128 bytes after the address x2 point to, but instead, it writes it exactly to the address x2 points to.

I also tried to use 64 instead of 128 but the same behavior was observed.

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