wavedrom / vcd Goto Github PK

Hello!

While I was testing the integration in TerosHDL and I have found this issue.
I have generated an VDC with ghdl for the same test in windows and linux. The linux generated file is correctly rendered, but windows' file not :(
After a quick investigation I think the issue is related with "new line" characters in windows.

I attach the generated VCDs. The results can be easily seen here: https://drom.io/vcd
wave.zip
/

I like this stream reader behavior, but it is overkill when the whole file is available. I just want a method, which gives back the fully parsed file, with all of the value changes.

I need a similar behavior to this, (just, that has some bug...)

Construct a new format while parsing the VCD file.
wavedrom/inspect#1

Compress while simulating

Decompress in Browser

• ZLIB : JS : https://github.com/nodeca/pako
• UNRAR : WASM : https://github.com/YuJianrong/node-unrar.js
• https://github.com/SteveSanderson/xzwasm
• https://github.com/LZMA-JS
• BROTLI : MIT
  • C : MIT : https://github.com/google/brotli
  • C : Apache : https://github.com/madler/brotli
  • JS : decoder + WASM encoder : https://github.com/foliojs/brotli.js
  • JS : decoder : https://github.com/google/brotli/tree/master/js
  • HAXE -> JS : MIT : https://github.com/dominikhlbg/BrotliHaxe (2017)
• Lizard

References

• https://bewilderedoctothorpe.net/2019/02/08/compression-comparison-archive-formats/
• https://github.com/inikep/lizard/
• https://github.com/facebook/zstd/
• https://github.com/google/brotli/
• lzbench an in-memory benchmark

https://en.wikipedia.org/wiki/IEEE_1164

Properties

• Compact
• Robust
• Scalable
• Extendible
• Fast

Ideas

Key Frame store

• timestamp
• array of pointers to every signal handler

Construct Range Tree to access Key Frames on the fly.

Vector of changes of a specific signal between keyframes.

Interval tree ???
Binary search tree ???
Red–black tree ???

/Users/runner/work/_temp/86caa96d-8769-4552-9a80-dc069d341bfa.sh: line 1:  1704 Segmentation fault: 11  npm run mocha_napi

https://github.com/wavedrom/vcd/runs/5726953627?check_suite_focus=true

Implement a more efficient way of looking up expected triggers.
Maybe https://en.wikipedia.org/wiki/Trie ?

Perl

• https://metacpan.org/pod/Verilog::VCD

Python

• https://github.com/SanDisk-Open-Source/pyvcd

C

Java

JavaScript

• https://github.com/ahmed-agiza/vcd-parser
• https://github.com/tcr/node-vcd

What is a good way of selecting signals from the large list?

• JSON Pointer
• https://github.com/jmespath/jmespath.js
• https://github.com/jsonata-js/jsonata
• https://github.com/json-path/JsonPath
• https://github.com/kriszyp/rql

$.change -- Extend Trigger EventEmitter to manage list of VCD triggers.

• manage VCD trigger list inside parser via standard EvenEmitter API

Hi,
Is there a VCD to WaveDrom converter available?

Thanks
Srini

• implement parser for VCD as described in : SystemVerilog 2017
• Implement parser tests
• JS bindings
• Test runner

Find a faster way of transferring bigInt from WASM to JS.

Register trigger callback with an event emitter.

https://github.com/wavedrom/vcd/blob/master/vcd_spans.c#L142

Current lazy way of parsing binary values:

int vectorSpan(vcd_parser_t* state, const unsigned char* p, const unsigned char* endp) {
  state->value = strtoul((const char *)p, (char **)&endp, 2);
  state->mask = 0;
  return 0;
}

It will brake on:

• literals longer then 64-bit
• literals with x and z in the body (not important for Veriltor, but important for 4-state simulators)
• real literals (low priority)

Proper parser should encode produce value and mask with data bits encoded the following way:

       0 1 x z
value: 0 1 0 1
mask:  0 0 1 1

use p.code.addMul(...) API

register callback on any change

Hey there,

I'm trying to get vcdrom to build and I am running into some build problems. Running make here results in:

bigdata~/p/w/h/v/vcd <3 make
make: *** No rule to make target 'vcd_parser.c', needed by 'out/vcd.wasm'.  Stop.

Write generator for constraint random VCD file with specific properties:

• Number of signals
• Total simulation cycles
• Change density
• Random seed

JS script?
C/C++ generator?

Verilog allows bit vectors or arbitrary width. Example wire [26:0] state
VCD dump state changes like b101010101010101010101010101
We need a compact binary form of storing such constants.

LEB128 option

MSB --------------------------- LSB
        101010101010101010101010101 27-bit raw binary
       0101010101010101010101010101 Padded to a multiple of 7 bits
 0101010  1010101  0101010  1010101 Split into 7-bit groups
00101010 11010101 10101010 11010101 Add high 1 bits on all but last (most significant) group to form bytes
    0x2A     0xD5     0xAA     0xD5 In hexadecimal
-> D5 AA D5 2A                      Output stream (LSB to MSB)

Verilog / VCD also allows 4-state values like: b10101zzzz01010101xxxx010101

That can be represented as mask value:

       0 1 x z
value: 0 1 0 1
mask:  0 0 1 1

Mask also can be LEB128 encoded.
In the case of a 2-state vector, mask will occupy 1 byte.

vcd2vcd the tool to filter:

• only needed signals
• only specific time range
• processing based on specific filter function