wallento Goto Github PK
Name: Stefan Wallentowitz
Type: User
Stefan Wallentowitz's Projects
magenta
Magenta Microkernel
metro-mpi
mgpio
Multi-bank General Purpose I/O
moodle_inscribe
Inscribe students into moodle courses by their email, even if the API is disabled.
mooreandmore
Data to print Moore's law
newlib
Newlib mirror
newlib-cygwin
Mirror due to connection problems
nexys4ddr
Open source and properly licensed code for the Digilent Nexys 4 DDR peripherals
openlane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
openlane-examples
Examples from the Openlane repository, adapted as Fusesoc cores
openrisc-basics
openrisc-landing
Draft for OpenRISC landing page
opensource-design-verification-workshop
Open Source Design Verification Workshop
opentitan
OpenTitan: Open source silicon root of trust
optee_os
Trusted side of the TEE
or1200mp
Multiprocessor variant of OpenRISC 1200 processor
or1k-ci-tests
OR1K Continuous Integration tests
or1k-gcc
or1k-src
OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)
or1ksim
The OpenRISC 1000 architectural simulator
or1ksim_reentrant
Reentrant version of the OpenRISC simulator
orpsoc-cores
Core description files for ORPSoCv3
ot-dsim
Bignum ISA Simulator
pandoc-beamer-how-to
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
pipeline-viewer
CPU Pipeline Viewer
pmod_switchbox
Pmod Switchbox
ponylink
A single-wire bi-directional chip-to-chip interface for FPGAs
pulp_vivado_ip
pulpino
An open-source microcontroller system based on RISC-V
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