Coprocessor stalls indefinitely if core issues random memory result transactions about vicuna HOT 4 CLOSED

Hi @moimfeld,

thanks for reporting. I believe the reasoning behind tolerating unrelated memory responses is that the XIF interface should be able to connect multiple coprocessor to a main core. Each coprocessor might then generate its own memory requests and should ignore any memory results that are destined for other coprocessors (by comparing the instruction ID of the memory result transaction with the ID used in its request).

As an initial step towards resolving this issue I have modified Vicuna's LSU such that it ignores memory result transactions unless it actually expects a result.

I also tried to ignore the result transaction if the ID does not match the expected value, but that currently leads to problems which I do no yet understand and will have to investigate further.

from vicuna.

Hi @michael-platzer,

Indeed, this rule makes sense in a multi-core environment.

Your fix resolved the problem of "infinite" stalls. Thanks a lot!
But as you mentioned, the coprocessor should probably also check if the id corresponds to the one of its request, or else it might store/accept wrong results.

from vicuna.

Hi @moimfeld,

this issue should now be fixed in 60ec4a7. Memory result transactions for which the instruction ID does not match the ID specified during the associated request are now ignored. Please let me know if re-enabling random memory results in your UVM environment causes issues.

from vicuna.

Hi @michael-platzer,

The infinite stalls are gone 😄. Thanks a lot!

from vicuna.