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aad2020_vvz_app_graldij_moimfeld

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

core-v-xif

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

This is the fork of CVA6 intended for PULP development.

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

hardware_schematic

opensbi

RISC-V Open Source Supervisor Binary Interface

otfusion

Model Fusion via Optimal Transport, NeurIPS 2020

socdaml_model

Model for socdaml project

vicuna

RISC-V Zve32x Vector Coprocessor