Comments (2)
Yes, that is correct. The operand width of each unit determines the amount of data that can be processed in one cycle but has no effect on the results. Increasing the operand width of a unit improves performance but requires more HW resources.
However, due to the way Vicuna fetches vector register, the maximum operand width of a unit is half the vector register width, i.e. VREG_W / 2
. Also, the minimum operand width is 32. Within these limits, the operand width of each unit can be chosen freely (although it must be a power of 2).
from vicuna.
Git it, thanks!
from vicuna.
Related Issues (20)
- Vicuna accepts instructions for which source registers are not valid.
- Wrong result generated by multiply unit (probably control logic related) HOT 1
- Wrong operand for `vwmacc(u|us|su).vx`
- narrowing instructions are never popped from the instruction queue HOT 1
- Vicuna + Ibex and WFI
- No way to clear a cache error?
- fail to set VREG_W=2048 HOT 2
- Floating point support.
- Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core
- 'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8
- Error in Questasim Simulation
- Reserved word not implemented: 'config' HOT 1
- Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model HOT 1
- Certain applications when executed with dual and triple pipeline configurations on verilated model of Vicuna hang indefinittely
- Applications hang indefinitely on Verilator when size of data cache is different than 0 HOT 1
- Suggestion for vectorizing MaxPool and Convolution Layer HOT 1
- Rounding issue for `vasub(u).(vv|vx)`
- Tail-undisturbed policy violation for comparison instructions.
- Masking not working
- `vslidedown.(vx|vi)` issue when VLMAX is exceeded
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from vicuna.