Simulation fails when memory width is wider than 32 bits without a DCACHE about vicuna HOT 3 CLOSED

Hi, sorry for the late reply.

The data cache indeed performs width conversion, and without a data cache, the data port width must match the memory bus width. As a temporary way to increase the data port width without using a data cache, I have added a parameter for the memory bus width. However, when a wider memory bus is used, an instruction cache is required to convert the 32-bit instruction fetch port of Ibex to the bus width.

You could now use a configuration as follows:

VREG_W=128  VMEM_W=64   VMUL_W=64  MEM_W=64 ICACHE_SZ=8192

I hope this works as a temporary fix while I come up with a more flexible way that allows port width conversion without using caches. Also, please note that the Verilator simulation currently only works with memory bus widths up to 64 bits.

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Thanks, I think another acceptable "solution" is to add an assertion, requiring the user to use a DCACHE or keep the bus widths the same.

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Wider memory bus widths are now possible even without an instruction cache, the only requirement is that the memory bus width must match the vector memory interface width if no data cache is used.

I have also added a bunch of assertions to catch invalid parameters.

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