Various VGA video output projects on the NIOS II processor, written in assembly.

The programs are designed to be compatible with Altera DE0, DE1-SoC, DE2 / DE2-115, and DE10-Lite FPGA boards.
So far, the code has been tested on the DE1-SoC and DE0-CV boards and is confirmed to be working.

In lower-left settings pane, disable: Device-specific warnings and Memory: Suspicious use of cache bypass

• Pong

  • Basic two player implementation
  • Switches 9/8 control left paddle and 1/0 control right paddle
  • Switch 3 is used to pause the game
  • Button 0 is used to restart the game
  • With SNES controller support, Up/Down control left paddle, X/B control right paddle, and Start / Select start, pause, and restart the game
  • With two SNES controllers, Up/Down on a controller controls that player's paddle, and both players must press Start / Select to start the game
  • First player to reach a score of 9 wins
  
  

• Game of Life

  • Minimal proof of concept implementation for now
  • Preset 2 glider pattern for testing
  • Button 0 is used to start the simulation
  
  

Pong

1. Figure out double buffering (done on 2018-03-09)
2. Implement some form of randomness (starting ball directions, etc...)
   • In progress (PRNG implemented but not yet used)
3. Make the score numbers the same size on different display sizes
4. Make the ball speed constant on all display sizes
   • In progress
5. Interface with one SNES controller (done on 2018-03-11)
6. Interface with two SNES controllers (done on 2018-03-19)
7. Add Pong AI

GOL

2. Optimize updates (tune memory access to increase speed)
   • In progress
3. Add boundry checking and wrap-around mode
   • In progress
4. Add random fill to init. playfield
5. Add other rulesets (in a general way)
6. Add colouring of cells