Comments (3)
Xilinx 7series have a Hard-IP on-silicon PCIe block so it wouldn't be in the sources except for the auto-generated stub core sources.
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So what you're saying is that the UR_CFG1 and the like are hard coded and are not configurable?
from pcileech-fpga.
That is not what I said. You asked how the PCIe IP was implemented and I answered it was a hard-ip block.
For additional information about the Xilinx PCIe IP core and its workings I can recommend the documentation at: https://docs.xilinx.com/v/u/en-US/ug477_7Series_IntBlock_PCIe
from pcileech-fpga.
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