Comments (2)
@ufrisk 请你帮帮我
from pcileech-fpga.
Hi, please understand that this is an open source project. As such I'm not really paid to do this except the quite few kind sponsorships I get.
I'll happily help out in fixing errors in the project code should you find any.
I unfortunately do not have time to give general free help/advice in how to code in verilog and how to use vivado. The error message says it's over-utilized. The 35T is a smaller chip and have less resources than the 75T. Your design seems to be too big to fit properly on the 35T. Maybe you can find ways to shrink it or maybe it's not possible. I don't know.
I'm however closing this issue since it's not really an issue with my software in this repo. Best wishes with your project.
from pcileech-fpga.
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