Comments (2)
AFAIU this is a bug.
from m2-isa-r.
This is indeed an oversight in the implementation of at least the ETISS code generator. CoreDSL type promotion rules are more or less ignored completely in M2-ISA-R as of now, therefore standard C type promotion rules are used in ETISS. I will look into this, but it will probably take a moment to properly fix.
from m2-isa-r.
Related Issues (19)
- slicing is not working correctly for extern variables HOT 3
- Sliced width is ignored during concatenation HOT 2
- Access of [[is_main_mem]] Memories does not work within functions
- Type casting HOT 1
- Memory read inside if-statement not generating correct code HOT 2
- PC access in functions does not yield correct results HOT 4
- return statement does not translate PC access correctly
- Memory access code generation needs an overhaul HOT 1
- Left-hand indexing not supported HOT 1
- Generate ETISS VirtualStruct for all registers HOT 1
- m2isar.backends.etiss.architecture_writer: Missing literal suffix
- m2isar.backends.etiss.instruction_writer: Missing literal suffix for slices HOT 1
- m2isar.backends.etiss.instruction_writer: Generatation of literals > 64bit HOT 2
- Include some examples / automated testing with github actions HOT 1
- Nested static statements HOT 7
- Index to Register File for Compressed Instructions not correctly handled HOT 4
- GDB Register Print Support in `RISCVVGDBCore.h` HOT 1
- Wrong code is generated in concatenation operation HOT 2
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from m2-isa-r.