EDA@TUM's Projects
CMSIS Version 5 Development Repository
repo to house various LLVM based SIHFT passes for RISCV 32/64 soft error resilience
CoreDSL descriptions of the Core-V ISA Extension (https://cv32e40p.readthedocs.io/en/latest/instruction_set_extensions.html)
Extendable Translating Instruction Set Simulator
SystemC/TLM2.0 productivity library wrapping the Extendable Instruction Set Simulator ETISS as a tlm cpu core.
RISC-V architecture models for ETISS
CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator
MiBench ported for IoT devices
Complete flow for keyword spotting on microcontrollers. From data collection to data preparation to training and deployment.
Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
TinyML model zoo primarily used by the MLonMCU python package
Target software library (MLIF, Machine Learning Interface) used by the MLonMCU python package
muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
CoreDSL descriptions of the RISC-V ISA
RISC-V Vector Extension v0.9 (RVV0.9) accelerated Gaussian Elimination for post-quantum McEliece cryptosystems.
Seal5 Project
Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.
Cmake modules for STM32, specifically for TFLM applications
Tiny machine learning demos for STM32 microcontrollers
Hello world TFLM example for STM32 boards
Implementation of `micro_speech` TFLM example running on STM32 Boards
Implementation of `mnist` TFLM example running on STM32 Boards