The repository contains VHDL lab exercises for bachelor course Digital Electronics at Brno University of Technology, Czechia. Nexys A7 Artix-7 FPGA board is used in the course.
- Vivado Design Suite 2020.2 (tens of GBs)
- TerosHDL 👍 (tens of MBs)
- ghdl + GtkWave (several MBs)
- EDA Playground (online simulator, 0 Bytes)
- ModelSim (several GBs)
- Introduction to VHDL and Vivado
- Combinational logic circuits
- Seven-segment display decoder
- Arithmetic circuits
- Binary counter
- LFSR counter
- FSM debouncer
- VHDL Project
- Basic gates in VHDL
- Binary comparator
- Seven-segment display
- Half/Full adder
- Clock enable circuit
- N-bit Up/Down binary counter
- Driver for 7-segment display
- One-minute stopwatch
- Traffic light controller
The following hardware and software components are mainly used in the lab.
-
Boards:
- Nexys A7 Artix-7 FPGA Trainer Board: reference manual, schematic, XC7A50T-1CSG324C FPGA, Nexys-A7-50T-Master.xdc
-
Analyzers:
- 24MHz 8-channel logic analyzer: software
- Oscilloscope Keysight Technologies DSOX3034T (350 MHz, 4 analog channels), including 16 logic timing channels DSOXT3MSO and serial protocol triggering and decode options D3000BDLA
-
Jeremiah C. Leary. Welcome to vhdl-style-guide's documentation!
-
ASHENDEN, Peter J. The designer's guide to VHDL. 3rd ed. Boston: Morgan Kaufmann Publishers, c2008. ISBN 978-0-12-088785-9.
-
CHU, Pong P. FPGA prototyping by VHDL examples. Hoboken, N.J.: Wiley-Interscience, c2008. ISBN 978-0-470-18531-5.
-
MANO, M. Morris. Digital Design: With an Introduction to the Verilog, HDL, VHDL, and System Verilog. Pearson, 6th edition, 2018. ISBN-13: 978-1292231167.
-
KALLSTROM, P. A Fairly Small VHDL Guide. Version 2.1.
React
Typescript
Django
Laravel
Facebook
Microsoft
Google
Alibaba
D3
Tencent