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openMSP430 project ported to Terasic DE0 and DE0CV. (I2C master core and basic UART included)

License: BSD 3-Clause "New" or "Revised" License

Verilog 62.10% Mathematica 0.03% Fortran 0.01% Tcl 29.38% Shell 2.12% Scheme 0.01% C++ 0.14% Batchfile 0.03% C 3.50% Makefile 0.23% SystemVerilog 2.25% Forth 0.21%
basic-uart fpga i2c-master openmsp430 simple-uart verilog

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