Related Issues (20)
- GHDL fails when testbench is inside a library (not work)
- Unable to rename elements
- Add "Stutter Mode" for Verilog/SystemVerilog, similiar with VHDL
- Syntax highlighting : parameter reserved word not highlighting
- Documenter: VirtualBus direction not recognized HOT 2
- Adding slang as SystemVerilog linter HOT 1
- The function of Autocomplete and snippets seems not work well on win11 HOT 1
- Quartus 23.1 fails to execute HOT 4
- Python3 binary path setting not taken into account HOT 3
- Undeclared net warning with xvlog linter
- State machine viewer broken since version 2.0.13 HOT 1
- The outline does not work well.
- Documentation isnt clear about using the syntax check
- GHDL Sample Project does not find library "mylib"
- Allow custom project definitions
- Inlay hints
- FSM image generator doesn't support conditional operator ( ? ).
- FSM image generator requires `begin` and `end`.
- Schematic viewer out put:[error] Yosys failed. HOT 7
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