- GitHub: github.com/Teddy-van-Jerry/sdr-psk-fpga
- Report: go.wqzhao.org/sdr-psk-fpga
Note
This is a course project of Southeast University (2023 Fall).
- BPSK/QPSK Modulation
- Coherent BPSK/QPSK Demodulation
- Carrier Synchronization (with Costas Loop)
- Symbol (Timing) Synchronization (with Gardner Loop)
- Packet-Based Communication
- Dynamic BPSK and QPSK Switching
- Pseudorandom (PN) Sequence Generator
- Block Diagram (with IP + Verilog RTL)
- Verified with Testbench
- Tested on SDR
- Pulse Shaping
You can explore details of implementations in the report.
Tip
The current design is resource-efficient. You have plenty of room to implement the remaining features to further enhance the platform.
- SDR: eNodeX 30B
- FPGA: Xilinx Zynq 7020 (xc7z020clg484-1)
- 1Tx-1Rx with GSM Antenna (Max 2Tx-2Rx on SDR but we only use 1Tx-1Rx)
- 4 GPIO as Output Signals (Max 8 GPIO Pins on SDR)
- Software
- Vivado 2022.2 (To directly open the project, you need version >= 2022.2)
- Matlab Filter Designer Toolbox (You can use alternatives to generate Xilinx
.coefiles) - LaTeX (My Version: TeX Live 2023 Latest)
- Python >= 3.9 (For Data Processing in Report)
This project is distributed under the MIT License. The report is open access under the CC BY-SA 4.0.
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