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Microprocessador-BIP-VHDL

Projeto feito para implementar o BIP em um FPGA

Diagrama do projeto

Diagrama_do_Sistema

Tabela OPCODE

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Descrição

Instrução Descrição
STOP Para o programa (HALT)
STO STO {endereço} salva o dado que esta no acumulador no {endereço} na RAM
LD LD {endereço} Carrega para o acumulador o que esta no {endereço} da RAM
LDI LDI {valor} carrega o {valor} diretamente para o acumulador
ADD ADD {endereço} soma o que está no {endereço} da RAM com o que esta no acumulador -} ACC = ACC + B
ADDI ADDI {valor} soma {valor} com o que esta no acumulador -} ACC = ACC + {valor}
SUB SUB {endereço} subtrai o que está no acumulador com o que esta no {endereço} da RAM -} ACC = ACC - B
SUBI SUBI {valor} subtrai acumulador com o que esta no {valor} -} ACC = ACC - {valor}
INP Carrega no acumulador o que esta nas chaves conectadas no FPGA

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